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 | |  | | | | | What Analog Issues Confront Designers of SoC Data Converters?
An interview with Eric Naviasky
Cadence Design Systems, Inc. | |
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Is it so difficult to correctly use these analog macros that I would need to hire an expert analog designer in order to place and interconnect them?
No. This common misunderstanding results from the simplified explanations that are often provided to management and procurement types. These simplifications are generally heavy on the macros containing black magic which implies the need to be handled only by trained professionals. In reality, any good SoC team should be able to successfully place and interconnect these devices if they pay attention to the special needs of the blocks.
I understand analog inputs of an ADC and the analog outputs of a DAC need to receive special care since they are analog pins. Should I treat the rest of the pins the same as I would for any macro?
No. Other very sensitive points are the references for the data converters, the clock inputs, the power supplies and grounds, and the substrate connections. In a well-designed macro the digital I/O are the only pins that are not too sensitive. In a not-so-well designed macro you need to worry about them also.
Are there rules about placement? Can I place the macro anywhere on the chip?
Not and enjoy life. The analog macros should be placed on the edge of the chip. This reduces the resistance of the lines to the pads and the opportunity for digital signals on the SoC to couple into the lines as they are routed to the pads. All blocks add noise to the substrate. The analog macros need to be placed in a "quiet "part of the chip. The chip edge tends to have less noise than the center does, since the macro is receiving noise from only one side. It should be noted that some digital blocks create more noise than others. Anything that drives large capacitive loads is particularly nasty and should be kept on the opposite side of the chip from the analog macro.
What about the I/O for the analog macro?
The analog macro often needs special analog I/O pars and ESD cells. The analog signals may not be able to tolerate the resistance or the capacitance of a normal I/O pin.
They may also need the I/O ring separated from the ring that serves the digital sections of the chip. The I/O ring supplies can pick up a large amount of noise through capacitive coupling from the digital I/O. To maintain the ESD protection, "break cells" with anti-parallel diodes need to be inserted where the ring is cut. Special low-capacitance I/O may be required for some of the pins to maintain analog performance; and some pins (e.g., crystal oscillators are a commonly missed case) need low-leakage ESD protection. High quality macros will often include the pads and ESD structures—or at least have suggested implementations.
Why do I need to worry about the reference pins? Aren't they just power supplies?
No. ADCs and DACs are ratio-metric devices. ADC's produce a digital output which is the ratio of the input to the reference. Any error (transient or static) in the reference can be indistinguishable for an input change (i.e., the error is weighted by the amplitude of the input signal). DACs produce an output voltage or current that is proportional to the product of the digital code and the reference. The reference needs to be as accurate and noise free as the desired output is. The reference is static in that it is not expected to move—but the currents drawn out of the reference pin can vary considerably with the signal input and the clock; therefore low-impedance bypassing is critical. A couple of ohms of resistance in the routing to the pad can degrade performance of a high-speed macro.
I have a clock tree (grid) that works fine for my digital design. Can I just hook up the macro to the same tree (grid)?
Probably not. An analog signal is defined by its value at a given time. The signal integrity is adversely impacted if either is wrong. If the signal changes slowly enough (i.e., the bandwidth of the signal is low enough relative to the sample rate), then the value may be the same at all times within the jitter space of the clock and the time error represented by the jitter is not a problem. If this is not the case, then the clock jitter has degraded the analog block. This is a characteristic of all sampled data systems and not a characteristic of the macro in particular. The only reason this shows up more in SoC applications is that there is the temptation to use the digital clock since it is near. This is not a problem for a digital signal since the data on the output of a gate is constant over the jitter space of the clock (assuming your timing was done correctly). The jitter requirement on the clock can be estimated by where the is the RMS jitter of the clock and the is the bandwidth of the input signal (not the clock rate).
How about the power supplies? The voltages are the same as I use for the digital core or digital I/O and I was going to tie them together at the board level anyway. Can I connect them on chip?
No. The power supply (ground is included in the list) pins of the macro have limited rejection of noise. The higher the common impedance the analog macro's power pins share with the digital section, the worse the noise problem. The best case is to have separate pins on the package for the power supplies for the macro which get their own bypass capacitors off chip and then join the power supply for the digital section.
None of this seems hard but there seem to be a lot of details to track. Is there an easy solution?
Yes. Some vendors will assemble the AFE into a super macro for you that includes the power, clock, reference, and input routing as well as the pads so that the only pins that need to be interconnected by the SOC team are the digital I/O.
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About the author
Only limited information is known about Mr. Naviasky's early life. Legend in the engineering community has it that he was raised by wolves during his early formative years. Evicted from the pack at age 7 when the wolves could no longer stand his sense of humor and poor table manners, he was apparently picked up by a misguided alien abduction team. Most of his formal schooling was accomplished in this "far offshore" fashion, though there is a record of a degree from Johns Hopkins University in the seventies. His career since the seventies has been a highly productive but random walk through the Bio-medical engineering, RF communications, and military-aerospace industries with an intense focus on analog and mixed signal IC design. In 1996 he was one of the co-founders of the Cadence Analog and mixed signal design practice. Since then with the careful attention of a team of handlers and damage control specialists he has been the driving creative force behind the organization and a continuous but necessary source of irritation to management |
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