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 | |  | | | | | Automated Custom Physical Design (ACPD) Flow
An interview with Johnny Premkumar
Senior CAD Engineer, National Semiconductor | |
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Tell us about your design team and their typical schedule, such as the length of your design cycle and the typical device size. How do you train them on new flows and methodologies if they are geographically dispersed?
Our design teams can range from ten to more than fifty people. Depending upon the complexity and size of the design, the project design cycle time is usually several months. This may include either test chips, products, or R&D related work.
We provide instructor-led courses, internal training, online tutorials, user guides, and training databases. We provide one-on-one phone support for off-site design centers as well as on-site demos, training, and in-person support. Users are directed to take Vendor training on specific tools and flows that may help them in their work. We also conduct seminars. The local designers as well as those from off-site centers attend these. Off-site design teams can dial in to the demos and seminars in order to participate in this real-time.
How do you approach "change management" when working to proliferate new design methodologies?
We educate users by providing them information on the benefits of the new methodologies. We provide validation documents using real design database. The validation provides a comparison of improvements by using the new methodology versus the old methodology. Improvements are shown in productivity, simplification of the design process, design optimizations, and automation. With this positive data in hand using real designs, we constantly encourage designers to try these new methods. User guides, design flow diagrams, and training databases are posted online for users to download. We also actively support designers while they try to adopt the changes in order to accelerate their learning curve as well as to direct them in the right path so that they are not overwhelmed by the details of the new methodology.
Tell us how you treat constraints in the overall flow. What is the benefit to the schedule by using formal constraints in the schematic/layout?
The formal constraints are determined and provided by the circuit designer. Formal constraints provide clarity for different parts of the design team and for CAD group which supports the designers in the design cycle. It saves time because at an early stage we can figure which constraints can be met, the priority of these multiple constraints, and which constraints may be conflicting. This places us in a better position as we try to satisfy the requirements of the circuit designer as well as the practical implementation, from a CAD perspective, and limitations experienced by the layout designers and the Back-end group.
You seem to take advantage of automatic device generation and placement technologies. Tell us how this benefits design changes during the layout process and how you manage those design changes.
We use the Automated Custom Physical Design(ACPD) flow as much as possible to our benefit. This flow helps to simplify and automate several steps in the physical design which otherwise would require several days of tedious work. We utilize advanced parameterized cells (pcells) to our designers benefit. This helps us to create a Design Rule Correct (DRC) device which is programmable and which also has connectivity information. Pcell requests are received from the designers. Based upon these requests and specification the pcells are developed. The availability of pcells enable the layout to be generated from the schematic instantaneously from the device level to the block level. Other features of pcells include automatic permute and abutment, stretching, chopping, and folding. The pcells enable a connectivity based layout environment which helps the designers to do better layout placement and automatic routing. Besides automatic routing, there is also the Virtuoso Custom Placer (VCP) tool which enables automatic placement of small digital blocks.
For device level analog designs, the Neocell analog place and route is utilized. This tool includes module generators to generate the layout from the schematic. Automatic transistor device inter-digitation, and resistor and capacitor arrays can be generated. The layout devices have connectivity. Also several analog constraints such as matching and symmetry can be applied to the design during automatic placement and routing.
So using the above schematic driven flow which provides automatic device generation and placement methodologies saves time from the tedious work of drawing, placing, and routing all of the layout manually. As the devices are already DRC clean and have connectivity to nodes, less time is spent in DRC and Layout versus Schematic(LVS) checking.
Your current flow does not seem to fully utilize a custom flooplanner. Do you believe a floorplanner can be used to create "proto-type" layouts? Do you envision using a floorplanner in the future, and why?
An extensive mixed-signal design Floorplanner would be helpful. Since Cadence has brought back support of the Virtuoso Preview Floorplanner we may look into adopting it for the future. We are yet to investigate all the benefits of incorporating this tool into our methodology. A Floorplanner would help to predict and assess the effects of physical layout before place and route thus enabling a top-down design flow. It would help the circuit designer to estimate the layout size, design, and performance at an earlier stage. The Front End design engineer would have more data to present to the Back End design engineer about design requirements. This would give the Front End designer more control and understanding of the physical design and in effect helps to optimize his/her circuit better. This would help to reduce iterations, save time, and in effect increase productivity to achieve a better circuit.
What tangible benefits have you achieved with the implementation of a connectivity driven Virtuoso XL flow and tools vs. manual non-connectivity layout?
The primary benefits are reduction of design cycle time and time to market, and more efficient use of layout resources. A schematic driven and connectivity based layout environment makes it simpler to do interconnects. Increased design sizes and complex designs can be handled with much more ease. Designers find it easier to do placements as they can view the connectivity fly-lines and optimize placements for lower routing lengths. DRC and LVS related verification and issues are greatly minimized as the designer has less chances of committing mistakes during interconnection. This greatly helps in productivity, and reduces tedious iterative work and de-bugging especially at the chip level. For dynamic design changes along the design cycle, the ECO cycle time is reduced as well as the updated connectivity and other design information can be derived quickly from the schematic. As a result, designers can re-direct this time saving towards design optimization and in effect produce a more optimal layout. Due to the design quality and productivity the manufacturing quality and yield is going to be greatly improved as well.
Read in more detail how National Semiconductor implements the ACPD flow: Automated Custom Physical Design (ACPD) Flow in Cadence IC5.0.x for Mixed-Signal Designs
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About the author
Johnny Premkumar works as a Senior CAD Engineer in the CAD Development Group at National Semiconductor. He has been at National Semiconductor for 6 years. He has a Masters in EE from the University of Southern California. Current work includes pcell development, Neocell technology file development, Layout Automation, support and usage of all ACPD related Tools, and development of design flows and methodology. |
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