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| | | | | | Interview: Turbo Technology Speeds Analog Simulation, Preserves Accuracy
The new Cadence® Virtuoso® Multi-Mode Simulation 7.0 release was released on April 10, 2008. To get a preview of the new software, cdnusers talked to Michael Tian, engineering director of the Virtuoso Spectre R&D team. Virtuoso MMSIM provides a complete suite of simulation products for analog, RF, memory and mixed-signal SoC designs.
Michael Tian,
Cadence Design Systems
| | Interview | | 04/28/08 | |
| | Interview: Key Features in Virtuoso 6.13 Release
The Virtuoso 6.1.3 release integrates the Cadence Space-based Router into the Virtuoso cockpit to help users work more easily with sub-90nm design. cdnusers talked with Steven Lewis to find out more about this release
Steve Lewis,
Cadence Design Systems
| | Interview | | 04/28/08 | |
| | Getting Plastered
Toumaz Technology has developed Sensium, an ultra low power wireless sensor interface and transceiver platform for a digital plaster style application that allows for remote real-time health care monitoring. Learn more about the analog/mixed-signal verification strategy based on Cadence Analog Design Environment and AMS Designer, that Toumaz has used for this complex mixed-signal chip to ensure first silicon success reducing the design time by 12 weeks.
Dr Alison Burdett,
Toumaz Technology Ltd
| | Technical Paper | | 04/16/08 | |
| | Model-Based Verification and Analysis for 65/45nm Physical Design
For 65nm technologies and above, manufacturability analysis and signoff was mostly limited to required and recommended design rule checks (DRC). For 45nm and below, we see a new methodology emerging: more complex manufacturability rule decks (MRD) to classify potential circuit or geometric violations ('hotspots'). Then, scoring rules are applied to predict overall manufacturability and prioritize hotspots for manufacturability improvement. Rule-based checking is enhanced with physical simulators, for simulation of random yield loss and of systematic effects, including lithography and CMP. This extended DRC concept promises sufficient accuracy at acceptable analysis performance. First implementations by different 45nm manufacturers are, however, based on separate MRD checking and simulation flows. IBM and Cadence are developing a software infrastructure combining MRD checking and yield simulation. Using a common interface, this software allows for flexible integration of different (including third-party) simulators and also for coupling different physical effects. For instance, CMP density violations are used to change lithography focus conditions. Or LVS-type connectivity analysis is used to calculate critical area for selected nets. The output can be used for signoff purposes, process optimization, or can be input to electrically-aware layout optimization tools. It can increase yield and reduce turnaround time by optimizing design and process windows. In this paper, we present more details on a first version of this architecture: an analysis flow combining MRD checking with random-defect yield analysis. This analysis flow includes software for automatic scoring of manufacturability hotspots and for generating input for automatic library and full-chip optimization tools.
Jason Hibbeler,
IBM
Daniel Maynard,
IBM
Sarah Braasch,
IBM
| | Technical Paper | | 02/14/08 | |
| | Virtuoso Passive Component Designer - integral part in Infineon's "Inductor on Demand" Design Flow
In today’s RF CMOS transceivers, integrated inductors and transformers are highly critical devices with respect to performance and occupied area. Each passive component needs to be optimized towards its targeted application and so the use of pre-characterized (measurement based) libraries with a fixed number of inductors is no longer sufficient.
Within the Infineon Inductor Design Flow planar on-chip inductors as well as transformers can be designed on demand by an IC Designer.
In order to quickly create and optimize the inductor / transformer, we use Cadence Virtuoso Passive Component Designer to synthesize the device with adequate speed and accuracy using a quasi-static solver. The flow allows creating an inductor / transformer layout pcell together with an equivalent circuit model within minutes. The model could be validated with the use of a full wave electromagnetic solver depending on how important the device is in the circuit. The on demand created models and layouts are LVS and DRC clean and can be used within an Assura RCX created extracted view for parasitic re-simulation.
The Inductor Design Flow has been applied in several successful VCO designs in order to create symmetrical and asymmetrical inductors. With the use of the flow a new first-time-right device is created. There exists no need for an inductor library in any technology. The device occupies the minimum available chip area and is always suited to the application and technology.
Dr.-Ing. Krzysztof Kitlinski,
Infineon Technologies AG
| | Article | | 01/07/08 | |
| | Interview: Virtuoso Passive Component Designer Now Supports Synthesis for Customer Pcells
Virtuoso Passive Component Designer provides a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. In this cdnusers interview, Bo Wan, VPCD Engineering Manager, briefly discusses the most important features.
Bo Wan,
Cadence Design Systems
| | Interview | | 11/16/07 | |
| | Using Thermal Analysis as a Tool to Aid Analog Floorplanning
Managing heat is important in high-power design; too much heat can cause higher current consumption and can contribute to reliability problems like electromigration and thermal run-away. The thermal map of a circuit can be used as a floorplanning tool to reduce heat, allowing transistors to operate in potentially more usable regions or to reduce temperature deltas in sensitive areas of the design; this may translate to lower operating currents, meaning greater efficiency. Electromigration is a function of temperature, so current densities in metal traces are typically derated at higher temperatures. Lowering the operating temperature can mean narrower power traces, potentially reducing interconnect parasitics. Gradient Design Automation's CircuitFire is a transistor-level analysis tool that operates within the Virtuoso environment on circuits with more than 100,000 devices. An extracted view is created from a DFII layout. The CircuitFire tool is then run, simulating the extracted view with either a DC operating point and/or a transient analysis. The thermal analysis tool runs successive simulations until a thermal steady state is achieved. The output of the tool is a heat map of the circuit under test. A designer can then look at the thermal map and make decisions about how the heat producing elements can be placed, and a new thermal analysis is performed. The simulation computes the heat for each device, and these temperatures can be backannotated to the devices, so that the thermal data is captured in the archived schematic.
David Schwan,
Sirenza Microdevices Inc.
| | Article | | 10/15/07 | |
| | Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately
Phase locked loops are essential blocks in most analog/mixed-signal and radio frequency applications today. Because of the complexity of PLLs, the different time constants involved, and the fact that the VCO frequency often oscillates several order of magnitude faster than the reference frequency, simulating PLLs at a transistor level presents multiple challenges and is extremely time demanding. Several approaches are available today using FastSpice simulation, behavioral modeling, or stochastic analysis. FastSpice simulators, by speeding up PLL simulation time, enable designers to characterize the PLL dynamics such as locking and settling time. Behavioral-model-based simulation approaches allow designers to tradeoff the various blocks characteristics and PLL performance by accelerating simulation speed. However, none of these approaches provides a successful noise analysis of the complete loop. Spectre RF recently introduced a new flow aiming to provide this capability. This flow includes a new model formulation for the voltage-controlled oscillator that predicts its dynamic behavior and captures the dynamics of oscillators due to VCO pulling, including injection locking and power-supply interference. In addition, the VCO model is automatically extracted from the transistor-level netlist, eliminating the need for additional calibration. This paper, awarded the People's Choice Award for Custom IC at CDNLive! Silicon Valley 2007, presents the Spectre RF noise-aware PLL flow within the Cadence environment and explores its strengths versus other existing flows. Several Integer-N PLL testbenches serve as experimental vehicles to validate the Spectre RF flow. The first section develops Spectre RF noise-aware PLL flow theory and use model. Section II presents the advantages of this flow versus other approaches available. Section III presents the experimental results.
Helene Thibieroz,
Cadence Design Systems
| | Article | | 10/05/07 | |
| | Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs
An automated flow has been implemented to detect printability hotspots using a model-based solution, and to automatically fix these hotspots during final routing optimization. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. Since the semiconductor industry is currently limited to 193nm scanners, no relief is expected from the equipment side and must come from the design side. Rule-driven routers fail to capture hotspots, as they are based on ideal polygons that do not represent the real silicon image. Model-based hotspot detection can validate design manufacturability and will account for complex two-dimensional effects that stem from aggressive scaling of 193nm lithography.
To enable this solution, manufacturing teams started to release model-based lithography checks; initially as a service using the manufacturing flow to check small cells, and now by releasing process information to designers for full-chip lithography hotspot detection. However, if manual fixing is manageable at the cell level, hotspot removal in large placed and routed blocks or even full chip is more challenging. Not only is full-chip litho/etch simulation required to have a reasonable runtime, but the fixing solution needs to be connectivity-aware and incremental with a very fine step size. This is required for a timing-aware solution that mitigates hotspots without adversely affecting timing closure.
This paper describes how fabless designers have integrated this hotspot detection solution in their design flow and how the hotspot removal flow efficiently removed most hotspots in real designs, thereby providing DFM closure.
Ed Roseboom,
AMD
Philippe Hurat, Ph.D,
Cadence Design Systems
| | Article | | 09/18/07 | |
| | Utility for Extracting and Highlighting Net Connectivity in Virtuoso
This paper describes the extensive benefits of having a custom, skill-based, net extraction utility. VXL probing, Mark Net and LVS extraction routines provide limited, if not buggy, net highlighting features. Our net extraction routine allows the user to hierarchically extract existing layout for VXL, perform ICC-like net highlighting in Virtuoso, compare net lengths, find shorts, cross probe with the schematic, and so on. The user can highlight nets by their name or select them in the layout if the name is not known. Nets can be selected, highlighted in multiple colors or emboldened. Highlighting can be canceled in progress or the user can highlight by area in the case of large nets. This is all done in an interactive skill utility without any batch processing.
Derek May,
Micron Technology
| | Article | | 08/06/07 | |
| | CDB to OA—The Migration Report
austriamicrosystems has migrated its well-recognized and well-established Process Design Kit, the HIT-Kit, based on Cadence software to the OpenAccess database and the Cadence Virtuoso platform 6.1. Migration of library data, Pcells, technology files, and skill routines brought up a number of issues such as the connectivity model used for Pcells, specification of vias in the technology files for different tools, and problems with the usage of the new streaming functionality. This presentation, winner of the Best Paper Award for Custom IC at CDNlive! EMEA 2007 and CDNLive! Silicon Valley 2007, gives an overview of the migration procedure including data validation, translation to the OpenAccess standard, and final verification of the translated data. Further, it gives detailed information about the challenges and pitfalls faced during migration and the in-depth cooperation with Cadence to finally ends up with a qualified HIT-Kit for Cadence 6.1 and OpenAccess.
Gernot Heiling,
austriamicrosystems
| | Article | | 06/12/07 | |
| | Virtuoso Multi-Mode Simulation 6.2 Improves Mixed-Signal Verification
At CDNLive! EMEA 2007 Cadence announced the release of Virtuoso Multi-Mode Simulation 6.2. cdnusers.org had the opportunity to discuss this release with Bruce McGaughy, Senior Architect for this new simulation technology.
Bruce McGaughy,
Cadence Design Systems
| | Interview | | 05/15/07 | |
| | Cadence Space-Based Router, the next generation
The Cadence Space-based Router won the EDN 17th annual Innovation Award last month. Cdnusers interviewed Stan Chow, Cadence VP of RandD for the Catena Project, about the router.
Stan Chow,
Cadence Design Systems
| | Interview | | 04/16/07 | |
| | Use of Virtuoso Layout Migrate for Layout DFM Optimization
DFM practices are currently being introduced in design flows in order to limit the effect of manufacturing marginalities. This paper, voted Most Valuable Paper at CDNlive! Silicon Valley 2006, will focus on physical DFM optimization using VLM. This paper addresses the following subjects: - Overall map of DFM activities at Freescale for 90 and 65nm nodes. - How physical DFM analysis inserts in that map. More specifically the paper describes: . DFM guidelines prioritization scheme . The use of a DFM checker based on these guidelines . Why this type of checker needs to report DFM layout improvability . The type of metrics that can be used to monitor and improve DFM quality. Why automated fixing is the next logical step after DFM quality measurement. More specifically this paper describes: . How a DFM autofixer was developed from VLM. . Results from DFM optimization process on 65nm layout, showing 2X to 6X improvement in DFM quality. . Functionalities that will be needed in further development of 'VLM for DFM'
Lionel Riviere,
Freescale Semiconductors
| | Technical Paper | | 09/19/06 | |
| | A Method of Identifying Analog Cell Mismatch Issues Caused by Photo Mask Misalignment
Most analog circuits are susceptible to mismatch. One source of the mismatch is the misalignment of layers on a wafer, e.g. between poly mask and active layers. For two MOS transistors placed as mirrored devices in the layout, if the poly misaligns perpendicular to the gate endcaps, the source and drains areas become unequal. These misalignments are acceptable for digital circuits, but can cause yield problems in analog circuits. Other sources of mismatch can be misalignment between Metal-1 and Poly, or between Metal-2 and Metal-1. Creating a layout that is insensitive to this form of mismatch is important to good yield. Existing physical verification flows do not catch mismatch errors due to mask misalignment. There are five possible combinations of any two layers, center, up, down, left and right. In this paper, winner of the People's Choice award at CDNlive! Silicon Valley 2006, a flow will be presented using Assura RCX to simulate the mask misalignments using the geomShift command. A script creates each of the desired layer pair misalignments followed by parasitic capacitance extraction to generate a spice netlist. A PERL script then looks at each node of each run and compares the base capacitance value for the net with the shifted mask capacitance. If the values differ, that node is marked as having a mask alignment sensitivity.
David Schwan,
Micro Linear
| | Technical Paper | | 09/19/06 | |
| | Managing Design Collateral Across Sites Using Perforce
This paper, voted People's Choice award at CDNlive! Silicon Valley 2006, discusses a process for effectively getting the CAD design collateral (like Process Design Kits, Skill, PCells, verification decks, etc ) into production for use by design teams. Many cad groups are formed by both ex-designers, tool folks, and an occasional software engineer. Design Collateral which is used by design teams must be both QA'd and released using a mechanism where accountablity and traceability are parmount. This problem gets compounded when mutiple sites are involved and ensuring the data is sync'd. This paper describes the process of using perforce to effectively manage the data, ensuring it's integrity by the design teams, and how the process of using it and SCM (Software Configuration Managment) tool aids in this process.
Steven Klass,
Standard Microsystems Corporation or SMSC
| | Technical Paper | | 09/19/06 | |
| | Higher Quality Designs - A Configuration Management Approach
In a demanding business environment imposing aggressive deadlines and strict timeframes for products' deployment, cutting down time-to-market by reducing products' re-spins and achieving high quality samples as soon as possible is essential. The challenge in complex chip architectures, such as Saifun's flash memories, lies in synchronizing between several cross-dependant sub-projects, from PDK translation, through custom circuit, logic and layout design, to verification and backend analysis. Consider ECOs and CAD tools modifications, and you get a dynamic, constantly changing environment, where changes need to be properly propagated without impairing work already done, an equilibrium that needs balancing for maximum productivity gain. In Saifun we met this challenge by creating a multi-design-flow environment based on strict methodologies enforced through policy checks, thus buffering between inputs and outputs of different flows and improving design quality. The system, which is implemented using Synchronicity's configuration management tools and integrated into Cadence's design environment, enables Saifun to successfully deliver several high quality products per year under a number of different 90n to 45n processes, in an aggressive 6 months to tapeout timeframe. This paperwill discuss the challenges mentioned above and the methodologies we devised to tackle them. Readers will share insights into advanced usage of Synchronicity's mirrors architecture (including features that where developed explicitly for Saifun), methods for implementing policy checks using DesignSync/DFII and ProjectSync, correlating metadata and revisioned objects, and integration with Cadence design environment.
Rom Bronfman,
Saifun Semiconductors
| | Technical Paper | | 09/18/06 | |
| | A Top Down Design Methodology for Mixed-signal Integrated Circuits using the VppSim Simulator
Mixed-signal circuits have entered mainstream design focus as heavily integrated communication chips have attracted large volumes within consumer markets such as the cell phone industry. However, despite the growing demand for such chips, design methodologies for achieving first pass silicon have been lacking. This session presents a top-down strategy for such design, and introduces VppSim as a tool for high level behavioral simulation based on C++ module descriptions. The use of C++ allows very fast simulation speed and highly configurable module behavior, and also allows seamless transition into digital and mixed-signal design flows using NCVerilog and AMS Designer, respectively. Using the presented top-down design methodology within the Cadence environment, we show four custom mixed-signal ICs which have achieved their desired performance in first pass silicon. These custom CMOS ICs correspond to a 3.6 GHz, low noise, wide bandwidth fractional-N frequency synthesizer, a 2.5 Gb/s, low jitter, clock and data recovery circuit, a 3.1 GHz limit amplifier with fast offset correction, and a new VCO-based continuous-time Sigma-Delta A/D converter. Readers will learn the strategies of how first pass silicon was achieved in these designs, and will better understand the benefits and limitations of behavioral simulation in general.
Michael Perrott,
MIT
| | Technical Paper | | 09/18/06 | |
| | Generating Abstracts for 65/90nm designs using IC6.1.0
Cadence Abstract Generator (AG) is widely used by designers to generate abstracts from detailed layouts in order to facilitate Place and Route flows. AG can generate abstracts in OpenAccess 2.2 and Lib Exchange Format (LEF). AG has been revamped in latest IC6.1.0 release to address design challenges at lower process technologies as well as for tighter integration with the Virtuoso and SoC Encounter design environment. The presentation showcases advanced blockage models, metal density calculation and new antenna models for 65/90nm technologies. Readers will be able to appreciate how these new features help resolve critical issues at these process nodes. The presentationl highlights the new AG GUI, fully integrated in Virtuoso environment. The presentation also provides examples of using AG from SoC Encounter environment natively. Readers will learn how to create abstracts with a single click and set some basic parameters to fine tune the abstract generation process. Custom block authors and library developers as well as digital designers will appreciate the ability to generate abstracts within their familiar environments. The presentation presents many other features like faster extraction for block power grids, supply and ground sensitivity for multiple supply and multiple voltage (MSMV) designs, support for gate array style cells and minimum area checks for pins. The paper also demonstrates greater flexibility in reading logical information using NCVerilog based verilog import. Readrs will also learn how to provide pin information using the Synopsys Liberty format.
Anshul Sharma,
Cadence Design Systems
Sanjib Ghosh,
Cadence Design Systems
| | Technical Paper | | 09/18/06 | |
| | User-friendly Pcell Interpretive Compiler
The demand for complex process design kits is increasing due to the need for timely new product introductions. Technology submircron dimensions advancements have lead to higher mask production costs and an ever increasing need for complex and quality process design kits delivered in a timely manner. Significant advances in the Electronic Design Automation (EDA) world have contributed to these growing requirements. Freescale's internally developed automation tools, Cadence's ROD and VirtuosoXL features are just a few examples of the effort attributed to improving process design kit development and enhanced contents. Yet, Parameterized Cell (PCell) generation continues to be a labor intensive task. A User-friendly Pcell Interpretive Compiler (UPIC) was developed to mimic the thought process of a pcell developer. UPIC scans a layout, identifies shapes, relative shape relationships, maps to corresponding pcell function and with minimal input from the user generates a scalable pcell. The pcell code is generated in minutes rather than hours or days that the more complex devices require. Adding parameters, labels, pins and specifying repeating shapes or repeating entire devices is easily accomodated in this GUI (Graphical User Interface) driven tool.
Julia Perez,
Freescale Semiconductor
| | Technical Paper | | 09/18/06 | |
| | A Modular PDK Regression Testing System
Many process design kit (PDK) developers perform regression testing to validate design kit updates. Brute-force regression testing involves manual interactions with the design kit and visual inspection of the resulting data -- a tedious and error-prone process. Some PDK developers have automated tests for a kit's various features, but in most cases the structure of the test is specific to the architecture of the design kit and therefore only reusable for design kits of the same architecture. Avago Technologies teamed with Cadence Services to develop a modular system for PDK regression testing. In contrast to traditional regression testing methodologies, this system is independent of the PDK architecture. Instead, tests are constructed based on the software tools the PDK supports and on key technology information stored in various formats. The tests generated by the system run in an automated fashion and create terse summaries of the detected differences. The PDK developer need only review the resulting summaries to discover behavior differences. The PDK regression testing system is composed of individual regression test modules (RTMs). Each RTM can be used in a standalone mode to test specific features of a given PDK, or test suites can be executed through a module known as the Regression Control Interface. The following RTMs are currently in production use: Assura DRC Assura LVS CDF Pcells Stream Technology file The Avago team has constructed numerous tests for their PDKs, bolstering confidence in the tested features and, in some cases, detecting problems that would have otherwise gone unnoticed.
Andy Weilert,
Avago Technologies
Jim Roucis,
Cadence Design Systems
| | Technical Paper | | 09/18/06 | |
| | A Flexible, Technology Adaptive Memory Generation Tool
Memories are by far the most dominating circuit structure found in modern day application specific integrated circuits (ASIC) and system-on-chips (SoC). When considering efficiency, it is not deemed good practice to create different memories from scratch for every unique ASIC. In an era where technology is ever improving and constantly changing, there is a need for versatile and technology adaptive memory generators. There are innumerable types of memory designs; in industry, large teams are often devoted to elaborate custom memories. This is generally not possible in academia, as resources and funds are limited, and tight deadlines push for simpler, scalable and customizable memory architectures. This paper discusses a design flow methodology for developing a memory generator capable of handling different memory designs and scaling across technology nodes. A highly automated flow, utilizing the power of Cadence SKILL scripting, allows for smaller teams to generate dense and efficient memory designs, as would be useful in academia. A generator is introduced for an IBM .18um technology, developed in 4 to 6 weeks, and is capable of being ported to different technologies by simply changing some technology specific parameters in the scripting. Readers will learn how to incorporate their custom tailored circuits into this automated design flow, showing the high customizability of this tool. Additionally they will learn to use Cadence Abstract Generator and RTL Compiler to incorporate this memory into a design flow for synthesis using Cadence Encounter. This methodology elicits a fast time-to-fabrication, customizable, reproducible and affordable solution for memory generation.
Adam Cabe,
University of Virginia
Dr. Wei Huang,
University of Virginia
Zhenyu Qi,
University of Virginia
Dr. Yan Zang,
Qualcomm
Dr. Mircea Stan,
University of Virginia
Garrett Rose,
Polytechnic University
| | Technical Paper | | 09/18/06 | |
| | Challenges of PDK migration from IC5.1.41 to IC6.1
A Process Design Kit (PDK) is a complete set of building blocks that are critical for any custom integrated circuit design. The elements of a PDK are schematic device symbols, simulation support, parameterized cell (Pcell) layout, tool technology files and physical verification rule decks. Currently most PDKs exist on Cadence version IC5.1.41 which is built on the Cadence Database (CDB). With the release of Cadence version IC6.1 which is built on the OpenAccess version 2.2 database (OA22), PDKs will require database migration from IC5.1.41 to IC6.1. This paper will explain the challenges of PDK migration and provide PDK developers with an overview of the required changes to develop and support PDKs in IC6.1 built on the new OA22 database. This paper will also offer suggested enhancements to PDKs to support new IC6.1 functionality that was not present in IC5.1.41. This paper should be part of a consecutive session of four PDK papers. The session will be moderated by Marco Racanelli (Jazz Semiconductor) and Maq Mannan (Cadence). Thr other papers for this session are: - SteP for testing IC6.1 based PDKs against IC5.1.41 based PDKs - Advantages of Generating IC5.1.41 and IC6.1 based PDKs using PAS - DFM enabled PDKs for IC6.1 using PAS
Andy Tran,
National Semiconductor
John Goelz,
Cadence Design Systems
| | Technical Paper | | 09/18/06 | |
| | An SOC Foundry Test Chip and Generic Design System Proof Point with Demonstrated Customer Success
The venerable concept of a generic design system targeting multiple technology variants and supporting complex mixed-signal SOC methodologies in order to consistently result in working silicon has been a worthy goal among universities, foundries, semiconductor designers, and EDA vendors alike for many years. Achieving such a specification-to-silicon generic design system, and incorporating diverse foundry libraries, silicon IP, and EDA tools and methodologies not only requires a symbiotic alignment of vision, but also necessitates close cooperation for the common good of the whole by all industry participants. In this paper, we present a concrete proof point, achieved after more than two years of focused collaborative effort, resulting in proven silicon. The pioneering design system contains a representative mixed-signal SOC test chip comprising a dual-tone-multi-frequency (DTMF) decoder/receiver, 400 Mhz PLL, self-bias current regulator, flash-based ADC, ROM, RAM, and a compact staggered I/O ring with multiple power supply domains fabricated with the 0.18um CMOS Tower Design Kit and libraries. Described are how the test-chip's designers successfully utilized multiple Cadence software platforms, including Incisive, Virtuoso, Encounter, and DFM with consistency throughout all design phases. We strive to detail this example of close mutual cooperation between the foundry, the semiconductor designer, and EDA suppliers as a seminal proof point for the industry to follow in the future as a whole.
John Gianni,
Cadence Design Systems
| | Technical Paper | | 09/18/06 | |
| | Disinherited Connections
Previous tapeouts which used inherited connections in Composer encountered numerous problems in LVS debug, due to power/ground shorts and wrong voltages being connected to multi-rail designs. While the use of implicit connections seemingly simplified design, the lack of visibility into the connectivity made it harder to debug. This session explores the next level of multi-rail methodology, doing away with netSet properties and reverting back to explicit pin connections; yet retaining the transparency and automation which inherited connections offered. A set of menus, CDF, custom Check and Save checks, and netlisting routines provide for the automation of explicit wire connectivity to power rails, allowing designers to automate their power grid design without removing their ability to customize and debug in a manner any different than debugging any other net. LVS debug time dropped dramatically in a future tapeout, due to designers being able to see their pin connections in the schematic as well as in the netlist. Methodologies for calculating the X-Y coordinates in a schematic for pins, instPins, wire stubs, etc. of power terminals is also explained--a problem not present when inherited connections are used. In the end, circuit designers need not manually route power connections--a problem for which inherited connections were designed; yet without the added complications to LVS debug--a problem which inherited connections introduced
James Roberts,
Qualcomm
| | Technical Paper | | 09/18/06 | |
| | Interview with Virtuoso 6.1 Platform Chief Architect, Bruce McGaughy
Following the announcement of the new Virtuoso Platform 6.1, cdnusers interviewed Bruce McGaughy, Chief Architect for the release. In this interview Bruce discusses what he thinks are the most interesting new simulation and analysis features of Virtuoso IC 6.1.
Dr. Bruce McGaughy,
Cadence Design Systems
| | Interview | | 09/13/06 | |
| | Constraint Driven Custom Design in IC6.1.0
Unlike the semi custom design which has a very well defined constraint driven synthesis, place and route methodology, full custom circuit design relies more on ad-hoc techniques to meet the design constraints. Different tools for circuit design, simulation, placement and routing, have their own constraint specification mechanisms. In some cases constraint enforcement and verification is a manual process. With the release of IC6.1.0 the full custom circuit design methodology will get a makeover. This paper will discuss the new front-to-back constraint driven design methodology unveiled by IC6.1.0. This paper will discuss following steps in this flow: - Specification of constraints in VSE-XL (Virtuoso Schematic Environment XL), and the use of these constraints to optimize the circuit in ADE-GXL (Analog Driven Environment GXL). - Automatic inheritance of constraint from schematic to layout, when layout is generated in VLS-GXL (Virtuoso Layout Suite GXL). - Use of constraints to place the design using Analog Placer or the Custom Digital Placer. - Use of the constraints to do constraint driven routing with Virtuoso Router. - Post layout simulations using parasitic extracted design. Use of features in ADE-XL/GXL to make sure that the design meets the original specification. This paper will explain how circuit designers can utilize the new constraint driven environment in IC6.1.0, to implement constraint driven full custom design in their design flow. The flow and the methodology discussed in this paper will increase productivity, and decrease the design cycle time.
Karun Sharma,
Cadence Design Systems
| | Article | | 09/13/06 | |
| | Interview with Virtuoso Platform Product Engineer Akshat Shah
Find out about the new Virtuoso Platform IC 6.1 from Product Engineer Akshat Shah.
Akshat Shah,
Cadence Design Systems
| | Interview | | 09/12/06 | |
| | Interview with Cadence IC6.1 architect, Don O'Riordan
Don O'Riordan discusses what he believes is the one most important feature of the new Virtuoso release.
Don O'Riordan,
Cadence Design Systems
| | Interview | | 09/11/06 | |
| | A Assura Geometry Extraction and Spectre Re-simulation fFow to Simulate Shallow Trench Isolation (STI) Stress Effects in Analogue Circuits
For CMOS technologies below 0.25øm Shallow Trench Isolation (STI) has become the standard device isolation scheme.
Despite its advantages, STI applies mechanical stress to the MOS transistor changing its electrical device characteristic. As the stress depends on local layout geometries, the stress has to be evaluated for each individual device. The bsim3v3 model has been enhanced and new instance parameters and equations were added to the model to cover this stress effects.
This presentation, from CDNlive! EMEA 2006, shows an approach how STI stress effects can be accounted for. The presented method is based on a Assura geometry extraction and Spectre re-simulation flow. For that the MOS transistors Component Description Format (CDF) were modified and additional commands were added to the Assura ‘extract rules‘.
Example layouts geometry were extracted and simulated and the influence of the stress effects were evaluated. As a conclusion appropriate layout techniques will be demonstrated to minimise STI stress for sensitive analogue circuits. This approach has been successfully proven at a 14Bit, 40MSps ADC design.
Bernd Fischer,
Xignal Technologies AG
| | Technical Paper | | 06/19/06 | |
| | Design and Simulation of Analog Baseband Processors Example: Analog LDPC Decoder
Analog baseband processors outperform digital signal processing solutions in terms of speed, area, and power consumption by up to several orders of magnitude. The example of an analog LDPC decoder with 135k transistors is used to highlight some design challenges. We present a design and simulation environment which extracts high-level simulation models based on circuit-level simulations in Virtuoso. These high-level simulation models facilitate system-level simulations in Matlab/Simulink for performance verification and optimization of various circuit-level parameters.
Matthias Moerz,
Aspien GmbH
| | Technical Paper | | 06/19/06 | |
| | Simulation of a Reconfigurable Mixed-signal Field Programmable Analog Array
Field programmable analog arrays (FPAAs) represent analog signal transfer functions which depend on alterable digital configuration data. For system-level design of filter structures as well as accurate transistor-level simulations of the analog transfer function, it is necessary to enter the respective configuration data. This presentation introduces a tool chain for replacing the chip's digital configuration logic with AHDL modules and OCEAN scripts in the analog simulation. A custom GUI allows entering of configuration data with a few mouse clicks and distributed simulation of parameter sweeps.
Fabian Henrici,
University of Freiburg
| | Technical Paper | | 06/19/06 | |
| | Co-simulation: Virtuoso AMS Simulators and Simulink (Mathworks) on Real Designs
The traditional bottom-up only approach for the design of RF, Analog and Mixed circuits can no longer handle increase circuit complexities and the need to be right first time. For new designs there is more and more mixture between Top-Down methodologies and Bottom-Up approach. For these new methodologies, informal communications between System Architect and implementation designers has to change. The co-simulation between data flow simulator and continuous time-conservative + event driven simulators could be the solution to make a real communication / interface between System and Design. Thanks to multi-competence expertise: Designers, System engineers, CAD and CTO engineers, EDA vendors (Cadence and Mathworks), we have succeeded in closing the gap between System and Implementation thanks to co-simulation. Our co-simulation pre-study concerns Virtuoso AMS Simulators (Cadence) and Simulink (Mathworks). Test cases coming from real designs will be presented. We began the study with a VHDL polyphase filter as a first vehicle in order to test the AMS Simulators - Simulink co-simulation. The second vehicle is a VHDL demodulator (GFSK modulation). For this second vehicle, we made run-time test and comparisons between the VHDL demodulator output and simulink input. The third vehicle is a 14-bit ADC where not only VHDL but also electrical transistor level co-simulation was required. Objective, technical details and final results of each test case will be summarized and as a conclusion. We will detail the main co-simulation objectives, difficulties and challenges in the RF, Analog and Mixed design flow.
Dr. Didier Depreeuw,
NXP
| | Technical Paper | | 06/18/06 | |
| | From Tools to Flow: Linking the Chains in a Cadence Reference Flow
Tower Semiconductor LTD is an independent Fab that provides its customers with full working Cadence Reference flow. Tower uses Cadence tools to build and maintain IP libraries and IP special analog design such as MicroFlash and Image Censor Pixels for it’s customers.
With today’s complex design flows FABs and CAD departments must focus not only on the correctness and workability of each tool but rather focus increasing attention on the orchestration of the entire design flow. This paper describes how Tower Semiconductor provides full roadmap from analog and digital pre layout simulation all the way through the layout design and to the final DRC and LVS till the post layout simulation using the extraction decks provided by Tower. The paper covers multi tool correlation examples like: RF flows, Automatic generation of environment for IP placement,and Memory compilers. The paper describes some test cases we use in order to find tool interface problems before our customers start to run smoothly their flows based on Cadence tool suites. Note:Powerpoint was presented at CDNLive! EMEA 2006, paper was presented at CDNLive! Israel 2005.
Ezra Cohen-Yashar,
Tower Semiconductor
| | Technical Paper | | 06/15/06 | |
| | Comparing UltraSim and UltrasimVerilog for Embedded Flash memory Development
Embedded flash memories are being integrated with both digital logic and huge parts of analog circuits. While the digital part of the memory can be designed with well known design flows, which includes pre- and post-layout simulations with NC-Verilog, the analog part needs rigorous simplification for effective simulation by using for example, Spectre. A post layout simulation of the complete memory by using this approach is impossible.
This paper, voted one of the best presentations at CDNLive! EMEA 2006, compares the performance of Spectre / SpectreVerilog with Ultrasim / UltrasimVerilog and describesthe difficulties in mixed-signal simulation with UltrasimVerilog. The design failure rate could be reduced by using nearly all schematic views from the design library during simulation and avoiding the need to have simplified circuits during simulation. The ability of a back annotation simulation for even large analog circuits is a major advantage of this simulator. A solution to have different simulation models for one Flash memory cell by selecting appropriate CDF parameter on its symbol is presented.
Holger Haberla,
X-FAB Semiconductor Foundry
| | Technical Paper | | 06/15/06 | |
| | Lithography-aware Design Enables "Extreme" RET
Advanced process technologies enable semiconductor companies to create ICs with new levels of performance and functionality. Yet, traditional methods for ensuring manufacturability of IC designs are largely ineffective at advanced nanometer nodes. To deal with sub-wavelength diffraction effects, emerging RET methods impose certain restrictions on the type of structures that can be reliably printed on silicon.
With the emergence of tools and methods that break down traditional boundaries between design and lithography, engineers can achieve optimum results in the shortest possible time. The continued evolution of design-aware lithography and lithography-aware design capabilities promises to offer increasingly effective strategies for ensuring manufacturability of more complex nanometer ICs. The PMF provides a new powerful database retainer for manufacturing information — used in upstream layout design tools — for a new and very sophisticated lithography-aware design environment.
Wolfgang Staud,
Cadence Design Systems
Bob Naber,
Cadence Design Systems
| | Article | | 02/13/06 | |
| | Improving Design and Manufacturing Through Design-enabled Lithography
Lithography has long been considered the bottleneck of the semiconductor manufacturing world. In reality, it has actually been the driver, and now supports the growth of the semiconductor industry. But optical extension has its price. Cost-of-ownership has always been the main driver behind technology decisions, and as long as multiple exposures stay below the cost of an EUV exposure, the main content of future lithography will be carried by EDA tools. But the EDA space currently suffers from one phenomenon that has plagued the mask industry for the past 20years: Besides the fact that it is the ultimate enabler, we have been unsuccessful in deriving the correct value from it. Just like maskmaking, the EDA content of lithography sits at or below the 1% mark of the overall industry volume. One thing for certain is that needs to change.
Wolfgang Staud,
Cadence Design Systems
| | Article | | 02/01/06 | |
| | Creating DFM Aware Pcells
Giovanni Bertoglio conceived the idea of a DFM compliant parametric
cells library as a result of the awareness of a missing link between the traditional design approach and manufacturing needs. Cadence interviwed Giovanni to find out more about where and when to use these DFM aware pcells.
An Interview with Giovanni Bertoglio,
ST Microelectronics
| | Interview | | 11/15/05 | |
| | A PCells Library and Routing Tool giving Designers the Option of a DFM Approach
The idea of conceiving a DFM compliant parametric cells library came as a result of the awareness of a missing link between the traditional design approach and manufacturing needs. This paper describes the need for this tool and how it works, with comparative graphs.
Giovanni Bertoglio,
ST Microelectronics
| | Article | | 11/1/05 | |
| | Verilog-AMS for Mixed-signal Integrated Circuits
Today's mixed-signal integrated circuits (ICs) are becoming increasingly complex as more digital and analog functionality merge together into one product. These complex ICs also are being developed according to more aggressive schedules than previous circuits. These two problems together require that mixed signal designers verify more circuit functionality in less time in order to quickly design a part that is production worthy.
One of the emerging tools that can help mixed-signal designers quickly design and verify the complex mixed signals circuits is Verilog-AMS. Verilog-AMS simulations using models that are carefully created can help define and verify architecture, drive analog specifications, verify connectivity and simulate an entire system in one mixed-signal environment. This paper will discuss some of the methods of creating Verilog-AMS models that will allow for faster simulations and higher quality mixed-signal designs. The paper will also discuss some of the benefits of using the Verilog-AMS simulator in doing digital development and chip level simulations.
The paper will show how Zilker Labs used Verilog-AMS to develop the design of a power management and conversion IC. Examples will also be included to show how Verilog-AMS aided in the digital development, in finding problems in the design at the chip and system levels.
Aaron Shreeve,
Zilker Labs
Marty Hood,
Zilker Labs
| | Technical Paper | | 09/23/05 | |
| | IR Drop and Electromigration Analysis with Ultrasim Power Network Solver in the VAVO flow
With CMOS process technology scaling down to 0.13nm and below, IR-drop and electromigation (EM) effects become significant design considerations. Decreasing power supply voltages due to IR drop, and signal degradation due to EM effects easily causes design failures which need to be analyzed early in the design process. Cadence?s Virtuoso Analog VoltageStorm Option (VAVO) and ElectronStorm Option (VAEO) powered by Virtuoso Ultrasim simulator power network solver (UPS) offer a complete solution for IR drop and electromigration analysis. Ultrasim UPS, a linear solver integrated into UltraSim, analysis dynamic IR and EM effects in analog, mixed signal, memory, and digital circuits. The required high performance and capacity is achieved by combining UPS with the advanced fast spice technologies built into Ultrasim.
In the VAVO/VAEO flow Ultrasim UPS is used as simulation engine while pre- and post-processing of the IR and EM data is done with VAVO/VAEO. VAVO analysis the IR drops in the power net, while VAEO checks for EM problems on signal nets. Both tools are integrated into the Analog Design Environment, and the extraction of the interconnect parasitics is performed with Assura RCX. VAVO/VAEO display IR drop and EM results as colored map in the layout, and as textual report, which allows cross-probing to the layout. Colored map and cross probing make it easy to debug and identify IR drop and EM problems. The paper introduces the VAVO/VAEO flow and the UltraSim UPS technology, discusses the IR drop and EM analysis features, and illustrates its application on a PLL design.
Dr. Kathleen Zhang,
Cadence Design Systems
Dr. Xiaohai Wu,
Cadence Design Systems
| | Technical Paper | | 09/23/05 | |
| | Increasing Productivity Through the Use of Layout Generators
As technologies get more complex and cells accommodate more features while reducing size, standard Parameterized Cells (Pcells) sometimes are just not enough. Designers could increase their productivity by having access to pcells with flexible outlines to fill arbitrary shaped available space. Examples include compensation capacitors and start-up resistors. This paper will cover algorithms for generating arbitrarily shaped layouts and different approaches on acquiring and manipulating process rules to create DRC correct layouts.
Michael Tabat,
Texas Instruments
Suzanne Kahn,
Cadence Design Systems
| | Article | | 09/23/05 | |
| | Design Conversion Tool
Modern IC design is strongly dependent from technology design kit (TDK) which is a central point of company technologists knowledge. Ideal compatibility between project database and TDK related Cadence library is a key feature of successful tape out. Any TDK update (models, primitives, technology specifics, etc.) could be critical for the project and causes painful design re-use. Comfortable checking and repairing of correspondent Cadence design database is a real need for design teams. Usually, special procedures/utilities for design migration are built-in TDKs or delivered separately. Since design update needs are appeared frequently there are problems with usage of correspondent migration utilities due to differences in program interfaces, initial settings, reports, etc. Moreover, the program development is complicated anytime by necessarily to create self-consistent procedures with own GUI, design hierarchy scanning, log information creating, etc.
SKILL based migration utility named as "Design Conversion Tool" was created to support customer needs for automatic design compatibility checking and repairing with emerged TDK. The tool allows check/convert Cadence design libraries easier, standard and quicker by separating of technology-independent core and technology-dependent plug-in set. Tool core presents common interface with GUI, plug-in registration and running mechanism, library scanning technique, summarizing issues and log data keeping. SKILL based technology-dependent plug-in is supposed to be applied on library, cell view or instance to determine design issues and fix them. Those plug-ins contain all technological specifics of checking/migration procedures. The tool could be used both for user defined checks to achieve own local goals and for common technology independent design update procedures like instance CDF compatibility checking, reference libraries checking, etc. Developed Design Conversion Tool presents unified design update flow. Unexpected and/or undesirable design modification is avoided by requirement to review and sign off discovered issues. Creation of procedures for design checking and repairing is dramatically simplified. The possibility to run multiple plug-ins simultaneously can greatly reduce the processing time of design update.
Sergey Yevstigneev,
Freescale Semiconductor Libraries and Memories Division
Boris Ryakhovsky,
MicroStyle Ltd. contractor for Freescale Semiconductor
Latyshev Valery,
MicroStyle Ltd. contractor for Freescale Semiconductor
| | Article | | 09/23/05 | |
| | An Advanced Mechanism for Plotting and Measuring Waveforms
Both of Cadence's waveform viewers rely on a system consisting of a results browser, waveform window, and calculator. This system, especially the calculator, has proved difficult for designers to adopt and use efficiently. The issue, in part, is due to the results browser or calculator acting as the hub of the plotting and measurement, while the designers prefer the waveform viewer itself to be the driver. In an effort to improve productivity during simulation analysis, both the calculator and results browser have been supplemented with complimentary tools. These tools may be used in addition, or as a replacement for the calculator and results browser.
The system, AgereScope, allows the user to quickly find and plot curves across multiple data sets. Additionally, it provides plotting options prior to the actual plot, such as color and modifier. AgereScope provides a quick and intuitive mechanism for making measurements on waveforms, made simpler by a cross-probing functionality with the waveform viewer. Advanced measurement capabilities have also been provided to make difficult measurements simple, such as the calculation of jitter. Additionally, users have the ability to create and load do files, which will recreate the plots and measurements on either the current or a new data set.
AgereScope has proven to increase designer product |
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