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 | |  | | | | | Creating DFM aware Pcells
An Interview with Giovanni Bertoglio
ST Microelectronics | |
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At which technology node should a person consider creating DFM aware P-cells and why?
The DFM oriented pcells library was created for a 0.13 micron technology.
The more the technologies become advanced and with higher density, the more such pcells can become useful, especially (as in my case) when a full custom design is required ,which involve not only the chip routing , but also the components as well.The final reason is a better yield which is proved to increase with respect to the traditional approach , as long as the techno becomes more sophisticated and dense.
How were you able to increase the complexity of the Pcell without sacrificing execution speed?
In my case the traditional pcell used to have about ten parameters.
The implementation of a DFM approach produced seven more parameters and we did not appreciate any significant execution delay.On the other side, it's also true that we do not dispose of any specific execution speed tests results.
Are their additional areas encompassed by DFM to which you believe this type of PCell application can be applied?
Another area where this type of pcells application can be useful is whenever one thinks about a DFM oriented routing approach which can find its natural complementation in DFM oriented components.
Can you summarize the specific process information that a person should have before writing one of these PCells.
The process engineer should give guidelines and suggestions for the specific technology. These guidelines involve the possibility to relax some rules, that means not to obey to the usual "minumum size" imperative.
They may concern for instance the spacing between contacts or the extension of the active areas,rather than the possibility to move contacts with respect to their relative layer. For any relaxed rule, precise limitations should also be clear.
The task of the person who creates a DFM compatible pcell is to judge when it is suitable to create to the user further boundaries in order to avoid the generation of cases with critical structures.
Read more about the creation of a pcells library and routing tool by Giovanni that will give designers the option of a DFM approach.
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About the author
Giovanni Bertoglio graduated in Engineering (Electronics) at the University of Pavia (Italy).
He joined ST Microelectronics in 1987 where he began as a designer of programmable logic devices. Later on he moved to the central R&D dept. where he is in charge of the development of pcells libraries for various Non Volatile Memory (NVM) technologies and tool flow for automated custom layout design.
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