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 | |  | | | | | Optimization of Yield Vs. Performance Variability
An interview with Shardul Kazi
Toshiba America Electronic Component | |
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What do you see as the biggest challenge in physical implementation today?
The biggest challenge in Physical Implementation today is DFM/DFY awareness. DFM/DFY is a must for designs based in sub-90nm process technology. Physical designs implementation need to be optimized based on process parameters and lithography for yield variability versus
associated performance variability.
What steps or measures has your design team taken to ensure that you can meet this challenge?
We address yield from the early stage of library development through out the design implementation process. Waiting until the post GDSII to mask stage to see if yield can be improved is too late and more costly and time consuming. We use On Chip Variation effects in our timing analysis to make sure that we improve timing yield. For improvement in the defect yield, we use double cut vias and special yield enhanced cells in the library. We also use wire spreading technology to improve yield during the physical design. The challenge is to intelligently select and use yield enhanced cells analyzing the balance between yield and performance.
How do you see this process evolving in the future?
This yield improving process needs to be automated. While the flows are being developed, engineers have to manually tweak the designs, replace the vias and cells and analyze the performance impact. We believe that this process will evolve with a deeper partnership between EDA companies and Integrated Device Manufacturers (IDMs)/foundries. With the deeper partnership, foundries' process technology and lithography parameters would be added to the design rules for EDA companies to use to optimize and automate the physical design tools in future. Unfortunately it is going to be difficult for foundries to form such deeper partnership with multiple EDA companies. Also, it is going to difficult for EDA companies to support multiple foundries very closely so it is essential for both the EDA company and IDM/foundry company to select a trusted partner and help each other.
What lessons have you learned from your experience in addressing this challenge today that may help other designers?
On improvement of timing yield, we had to spend a lot of time during timing analysis with and without SDF, OCV etc. For improvement on the defect yield, our experience of inserting double cut via concurrent with routing showed that we get higher double cut via ratio versus inserting double cut vias on the post route basis resulting into related performance impacts.
Find out more about the Toshiba tapeout.
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About the author
Shardul Kazi is the vice president of the Embedded Processor SoC Business Unit at Toshiba America Electronic Components, Inc. (TAEC). In his current position, he is responsible for marketing, semiconductor, systems, and software engineering and profit and loss activities. Prior to that, he was chief operating officer and vice president at ArTile Microsystems, Inc., a TAEC spin-off. Before that, he was vice president of Microprocessor engineering at TAEC. With more than 20 years of semiconductor industry experience he has held various senior management and engineering level positions at other companies like Adaptec, SONY, MIPS and AMD. He holds a Master of Science degree from the University of Wisconsin.
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