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| | | | | | Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure
In this paper, we describe the use of Cadence Chip Optimizer for design closure in conjunction with SoC Encounter GXL-based place-and-route flows. We present a few innovative scenarios including yield optimization where Chip Optimizer could be used for design closure. In particular, we elaborate on our experiments in achieving timing improvement, shorts/design rule violations reduction, and yield optimization using Chip Optimizer. Using Encounter technology as the primary place-and-route tool, we describe in this paper our flows for seamless data integration with Chip Optimizer and optimizations performed as ECOs to the design. We find the design flow that includes both Encounter technology and Chip Optimizer to be very promising in these scenarios and provides a significant productivity leap over existing flows. These optimization scenarios are more relevant in the context of high-speed 65nm designs, where foundry rules are very complicated and it is important for any back-end CAD tool to comprehend all the rules and preserve timing while fixing them.
Narayanan Thondugulam,
P.A.Semi
| | Article | | 03/05/08 | |
| | Routing Based Yield Optimization Preserving Timing
The methodology presented in this paper, presented at the SAME conference in Sophia Antipolis, France, is able to apply different kind of optimizations according to the criticality of nets. Timing budgeting is performed to determine critical nets. Budgeting is natural choice since at this level of the flow a trial and error approach is too expensive in term of CPU.
Pierre-Olivier Ribet,
Cadence Design Systems
Salvatore Dario Minonne,
Cadence Design Systems
Olivier Omedes,
Cadence Design Systems
| | Article | | 11/02/07 | |
| | The Art and Science of Pin Placement for Hierarchical Floorplanning
The quality of pin placement for blocks and partitions can make or break the quality and time to market of a hierarchical design. Proper pin planning with careful attention to detail can improve the quality of results (QoR) in just about any aspect of large integrated circuit designs. The Cadence Encounter floorplanning application provides numerous tools for the chip floorplanner to control pin placement ranging from the automatic to full manual control. Due to the complexity of the interactions between these tools and the varying QoR provided by them over the maturation of the application, it is important for the user to understand the subtle and not-so-subtle issues involved. This presentation, winner of the People's Choice Award in Digital Implementation at CDNLive! Silicon Valley 2007 first covers motivations for and the basic concepts of pin placement, and then quickly moves on to more advanced topics covering the breadth of Encounter capabilities and limitations. Avago Technologies' proprietary extensions are reviewed, and the presentation closees with a review of the Encounter pin editor's vastly improved QoR, performance, and capabilities rolling out in current and future releases. These new capabilities were developed through a joint collaboration project involving Cadence R&D and Avago Technologies.
Jack Benzel,
Avago Technologies.
| | Article | | 09/27/07 | |
| | Interview: Making Reliable Models for SSTA
Prashant Maniar, co-founder and chief strategy officer of startup Stratosphere Solutions, Inc, includes guiding the company to meet customer needs, partnership building, coffee making, network wiring, and furniture moving as part of his day-to-day job description. After talking to him, we don’t doubt his energy to do it all!
Prashant Maniar,
Stratosphere Solutions, Inc.
| | Interview | | 09/10/07 | |
| | Debugging Clock Trees Will Now Be Easier
In the RTL world, clocks are ideal signals with few difficulties. However, during the implementation phase, when the clock tree is built and clocks are switched to the propagated mode for static timing analysis, problems start to appear. At NEC Electronics, a lot of designs come from external customers who rely on NEC for the layout. Implementation engineers must then capture and translate designer intent into specifications for the clock tree synthesis tool, and at the end they must ensure that the actual results fit with the expectations. Unfortunately, there are many different barriers to obtaining the desired results. Understanding the cause of a long clock latency, a synchronization problem between clocks, or an unexpected clock gating setup check is often time-consuming and causes delays in the project schedule. NEC turned to Cadence to help address this issue. The basic requirements were a graphical environment that would visualize the whole clock tree so that its structure would be easy to understand. The display should be similar to a schematic and the timing of the clock tree should be immediately obvious. At the end of 2006, Cadence delivered a prototype of the clock tree analyst in the SoC Encounter system that NEC started to use on real designs. Very quickly it allowed us to successfully debug several issues met on current designs. The main goal of the presentation is to explain how such a tool helps to debug clock tree implementation issues.
Martin Spohr,
NEC
Frank Guffler,
NEC
| | Article | | 07/2/07 | |
| | Encounter 6.2: Reduce Duplication and Minimize Power Domain
The release of Encounter 6.2 brings both feature maturation and new features to digital IC designers. In this cdnusers interview, Mui-Chwee Tong, Cadence product engineer lead, briefly discusses the most important features.
Mui-Chwee Tong,
Cadence Design Systems
| | Interview | | 04/04/07 | |
| | An Innovative Flow to Implement Large Scale Design Changes in the Final Stages of Physical Implementation
A technique to implement large scale RTL Engineering Change Orders (ECOs) in System-on-Chip (SoC) designs at their final stages of physical implementation is presented. The technique aims at minimizing the design cycle time for implementing critical-path ECOs that affect large parts of a design so that designers are able to incorporate such changes without causing a major schedule impact. The proposed flow was successfully implemented and tested on a 90nm wireless Application Specific Integrated Circuit (ASIC) design that was first-pass success on silicon.
Manoj Kumar Dadhich,
Freescale Semiconductors
Vajeed Nimran,
IIT Mumbai, India
Amit Bandlish,
University of Southern California, US
| | Technical Paper | | 10/29/06 | |
| | Handling Design Variability through Encounter SSTA
With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. Conventional static timing analysis using best case/worst case analysis is overly pessimistic, and could be optimistic also in some cases. This has resulted in the promotion of Statistical Static Timing Analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. The key functions that need to be enhanced or modified for doing SSTA are: * Characterization - To capture the effects of transistor process parameters variations on library generation * Extraction - To capture the effects of interconnect process parameters variations on parasitics extraction * Reduction - For generating a reduced order model of the variational interconnect * Delay Calculation - For computing the variational delay of the design * Timing Analysis - For determining the slack of a path as a distribution and for computing the criticality of a path as a distribution function In this paper, we describe the rationale behind using SSTA, SSTA modeling requirements and Cadence's SSTA solution (Encounter SSTA). The SSTA modeling requirements have been handled through Sensitivity Extension to ECSM and SPEF (the new formats are known as S-ECSM and S-SPEF. Cadence's existing tools viz. SLC (characterizer), QRC (extractor), SgS (delay calculator) and CTE (timing analyzer) have been enhanced and a new reducer (VMOR) has been developed to provide a comprehensive SSTA solution. In this paper, we will also discuss the use of SSTA in design implementation.
Parveen Khurana,
Cadence Design Systems
| | Article | | 09/19/06 | |
| | Designing Out DFM Issues at 65 nm
As technology nodes get smaller, feature limited yield is becoming the dominant yield factor
over defect limited yield. Leading edge physical design involves having a strategy for dealing
with these DFM and yield issues while still adhering to strict time to market deadlines.
This presentation, winner of one of the Best Paper awards at CDNLive! EMEA, describes the methodology developed by S3 to successfully address 65nm DFM implementation issues in the physical design flow. To illustrate this methodology,
S3 refers to a recent 65nm design examples operating at speeds up to 500MHz.
S3 were responsible for all aspects of the design flow including synthesis, floorplanning, PnR,
DFM, Static Timing Analysis, Physical Verification, Crosstalk Analysis and Power Analysis
The tool-set included RTL Compiler, SOC Encounter, PrimeTime, Calibre, Conformal,
VoltageStorm and in conjunction with S3's NanoFlow design environment.
The key challenges encountered are addressed, including DFM Power Grid Insertion, Signal
Routing and lagging tool capabilities
Sarah Lamont,
Silicon and Software Systems (S3)
| | Article | | 06/27/06 | |
| | Using Correct Timing
How NEC brings Encounter Timing System to Sign-Off. Correlation of Timing Constraints and Timing Calculation between the STA Signoff Engine and the Timing Optimization Engine is essential for a reliable schedule. NEC drives the Encounter Timing System to fulfill these requests
Martin Spohr,
NEC
| | Article | | 06/23/06 | |
| | Encounter SmartKit: the Digital On Top Implementation Platform for STMicrolectronics SmartPower Applications
SmartPower, also known as “BCD”, in one of the main process families used at STMicroelectronics. Its main feature is the integration in the same chip of CMOS, Bipolar and Power DMOS devices, supporting up to 90V. This is the ideal process for applications requiring High Voltage / High Power capabilities, together with traditional digital logic, in particular products for the Automotive and Computer Peripherals (Printers and Data Storage) Market. Due to the special nature of the process, a Digital Implementation Flow for SmartPower designs requires special attention to specific needs like irregular Block Shapes for Digital IPs to be assembled at the top-level, with very challenging block pin management; Usability of the Environment must meet the needs of the particular user’s profile, an Analog / Mixed-Signal physical designer, with a strong full-custom expertise.
Lyes Djama,
ST Microelectronics
| | Article | | 06/23/06 | |
| | Implementation of the SoCDE flow in FMS - the Flow Developer's Perspective
The aim of this presentation is to discuss the development effort for converting the current release of the SoCDE flow into an easy to use, comprehensive automated flow solution implemented in FMS The scope of the presentation extends to the following topics:
a short overview of the SoCDE flow tasks and in particular the ones subject to automation;
a review of the latest FMS release and its essential features for the automation of the backend design practice in Philips;
a discussion of the SoCDE flow automation procedure with respect to the FMS specifics;
an analysis of the FMS performance results when tested on different test cases (blocks from VMIPS and PNX8535)
a debate over specific problems of the SoCDE flow customization under FMS.
Finally the talk address some problems and solutions that FMS developers and users encounter in their daily work. The presentation concludes with short discussion over the presented aspects the SoCDE FMS flow solution and suggestions for future FMS/flow improvements.
Dimitar Kavalov,
NXP
| | Article | | 06/23/06 | |
| | Experiencing Encounter Solutions for Low Cost Products
To be competitive on the market of "low cost and high volume" products it's extremely important to reduce the single chip cost. To achieve this target it's necessary to take advantage of new Deep Sub Micron (DSM) technologies, to grant die area reduction and a larger number of die per wafer, but at the same time the manufacturing cost of the latest 6-8 copper metal layer DSM processes is definitely unaffordable for this kind of products.
To overcome this problem it's now growing the demand to move to DSM processes with a limited number of copper metal layer (3-4) in order to reduce the wafer cost saving money for mask set.
In the field of chip assembly this choice brings to face old problems of routing closure and gate density degradation due to the lack of routing resources.
Unfortunately CAD vendors are usually more interested to address the new complex issues of the incoming DSM technologies and to target the performance of their new tools on million gate high end application than to focus on low end low cost products.
This presentation presents how we faced these issues in STMicroelectronic using the Cadence Nano Encounter solution.
Davide Casalotto,
ST Microelectronics
| | Article | | 06/21/06 | |
| | Fast and Accurate Statistical Cell Characterization with Spectre
Statistical timing analysis is an emerging technique that addresses increasing process variation effects on circuit behavior for designs at 65nm and below. Accurate statistical timing analysis needs accurate statistical cell models, which in turn requires a new approach to cell library characterization. A statistical cell characterization system must adequately capture the effects of variation, while simultaneously maintaining fast turnaround time to avoid being the bottleneck in the statistical analysis flow. This session will describe a seamless library characterization methodology that bridges the traditional needs of deterministic timing analysis and the new requirements of statistical timing analysis of process variations. A new statistical cell characterization system that simultaneously models the systematic and random variation effects on timing, power and noise will be described. A unique "white box" characterization approach that performs transistor level circuit analysis of process variations will be introduced. Powerful runtime reduction techniques resulting in 100 fold characterization time reduction while preserving modeling accuracy will be presented. A case study utilizing a commercial cell library characterization system together with the Spectre circuit simulator will be presented. The attendees will learn a proven statistical timing analysis flow comprising of existing library characterization, statistical timing analysis and circuit simulation tools. Results and benefits from using this new methodology will be presented.
Ken Tseng,
Altos Design Automation
Michio Komoda,
Renesas Technology Corp
| | Article | | 04/04/06 | |
| | Manufacturability Studies of X Architecture Diagonal Lines
This paper, presented at DesignCon 2006, addresses the manufacturability, yield, and reliability aspects of X architecture interconnects (diagonal lines) in a VLSI design that enables IC chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130nm and 90nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan vs. X architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X architecture designs.
Narain Arora, PhD.,
Cadence Design Systems
Kalyan Thumaty,
Cadence Design Systems
| | Article | | 02/27/06 | |
| | Designing a Real-time HDTV 1080p Baseline H.264/AVC Encoder Code
The hardware implementation of the emerging H.264/AVC video compression standard
presents a number of difficult challenges when it comes to real-time encoding at HDTV
rates. This paper, presented at DesignCon 2006, describes an efficient implementation of a baseline H.264/AVC encoder
core capable of encoding a 1920x1080 video stream in real time at 30 frames per second
(HDTV 1080p). A very favorable comparison with the JM 8.6 software reference model
also will be presented. While the specific target of the design was HDTV 1080p, the
small size and low clock frequency required make this core suitable for a variety of
applications, from mobile communication devices to HDTV camcorders and video
surveillance systems.
Vincent Liguori,
Ocean Logic Pty Ltd.
Kevin Wong,
Ocean Logic Pty Ltd.
| | Article | | 02/27/06 | |
| | Design of a 400MHZ DDR2 Memory Controller for a High-performance CPU Application
High-Performance CPU applications are one of the most demanding for memory
controllers. The overall system performance can be significantly reduced if the memory
controller can't provide memory accesses fast enough to keep the CPU running at top
efficiency.
This paper will discuss the key requirements high-performance CPU applications put on a
memory controller and will explore several tricks and techniques used to address these
requirements.
Raghavan Menon,
Ingot Systems
Warren Miller,
Ingot Systems
| | Article | | 02/23/06 | |
| | "Fearless Partitioning": An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SoC
This paper presents a design methodology with associated implementation techniques that helps cope with the complexity of integrating existing parts into a single die. These techniques have successfully been applied on a complex SoC built from four existing devices together with additional new functionality. It was demonstrated that "breaking the logical hierarchy" to better fit the physical implementation can lead to significant advantages. Combined with "correct by construction" approach and optimized floorplanning methods, it can facilitate fast automatic iterations and improve time to market drastically.
Herve Menager,
Philips Semiconductors, San Jose
| | Article | | 2//5/05 | |
| | SoC Encounter Provides Smart Solution for 90nm Dragon-Ball Chip
By employing the solutions provided by Cadence SoC Encounter (SOC.41), the physical integration team at Freescale Suzhou division has developed a smart semi-automatic physical implementation flow. This environment employs the technologies developed in Encounter to address the challenge of physical partition implementation with respect to the key factors of area, timing, power, and signal integrity.
This flow has been successfully used to perform physical implementation of a System-On-Chip Dragon-ball product designed in 90nm technology with 7 metal layers involving 5.5 millions of gate-account. The robustness and the capacity of the flow is an asset with regards to the size of physical partitions and the aggressive time-to-market pressure. And it gives designers a very accurate control of runtime against of Quality of Result.
This paper discusses the whole flow, which includes from hierarchical floorplan by First Encounter; chip level clock tree generation by Encounter-CTS; signal route by NanoRoute; and post optimization and SI fix by Encounter.
Wei Sufen (Stella Wei),
Freescale Semiconductor, Wireless and Mobile Sector
| | Article | | 11/23/05 | |
| | Library Characterization - the Cornerstone to 65 nm Timing Analysis
In this interview, Vincent Ross discusses delay calculation in relation to Static Timing Analysis. Vincent's interview text is augmented by an audio interview that discusses these concepts in more detail.
An interview with Vincent Ross,
ATI Technologies
| | interview | | 10/11/05 | |
| | Pre-route Net Classing for Crosstalk Avoidance
Inter-wire coupling continues to become a more significant portion of the total wire capacitance in deep submicron designs. Coupling introduces noise that has 2 important aspects: functional noise and delay noise. Additional delay causes timing closure problems, and noise destroys signal integrity. Fixing functional and delay-noise violations are time consuming however, due to the iterative routing and analysis need with current crosstalk-avoidance design flows. The ultimate goal for crosstalk avoidance routing is to reduce delay uncertainty as well as coupling noise so that users can eliminate a lot of iterations between routing and post layout fixing. This session presents a method called "net classing" to avoid both types of noise during the global routing phase. The basic idea is to have a global view of interconnect behavior so that they are routed in a correct sequence. This session creates a path analyzer to identify timing critical nets and a coupling analyzer to identify noise critical nets. This session feeds the net class information generated by a global router into a commercial tool to complete detail routing and noise analysis. All the analysis is done with Cadence Design tools except the net classing scheme. CeltIc analysis of detail-routed results showed that net classes help reduce timing uncertainty by 5% and maximum noise peak by 43% on average with an acceptable runtime which is comparable to a crosstalk avoidance routing flow but with much less human interaction. The current comparison is done in a 0.25 um bulk CMOS technology. This session is characterizing cell library in a 0.13 um bulk CMOS technology and a 0.18um SOI 3D CMOS technology to see the net class' impact on more advanced technologies and circuit topology. This method expects more reductions in advanced technologies.
Hao Hua,
North Carolina State University
| | Article | | 09/23/05 | |
| | Current Based Delay Models: A Must for Nanometer Timing
In order to accurately account for nanometer effects during timing analysis, existing cell models must be replaced. The assumption of linear input voltages and lumped output load are no longer valid. Further, the existing delay models do not match well with the advanced interconnect delay models. Interconnect models consume linear voltage waveforms produced by these cell models and produce voltage waveforms for consumption by downstream cell models. These interconnect models are well suited for the approximations created by existing cell models but do not scale well when used in conjunction with more complex input voltage waveforms. Furthermore, the arbitrary waveforms produced by these interconnect models are linearized for consumption by these cell models. Current based delay models circumvent this problem and provide a cell delay model which can both produce and consume non-linear voltage waveforms. This paper discusses the need of delay modeling for nanometer timing analysis, how nanometer delay calculation issues are addressed with these new modeling techniques, compares the various models and shares experimental/field results using ECSM models.
Ratnakar Goyal,
Cadence Design Systems
| | Article | | 09/23/05 | |
| | A Standard RTL-to-GDSII Design Methodology for System LSI in 90 nm and Below
A recent system LSI in an advanced process technology such as 90nm and below is complicated due to integrating much more functionalities. In implementing the system, LSI from RTL to GDS2, the most critical design issues are, along with timing closure, signal integrity and design for manufacturability (DFM). This paper describes RTL-to-GDS2 design implementation methodology, called the STARCAD-21, which enable it to achieve first silicon success and shorten design turn around time drastically
Nobuyuki Nishiguchi,
Semiconductor Technology Academic Research Center (STARC)
| | Article | | 09/23/05 | |
| | Thermally Aware Design Methodology
With process technologies at 90 nm and below, electro-thermal effects are becoming a dominant source of IC performance, power and long-term reliability problems. Today's design methodologies, which assume a constant temperature, miss catastrophic design errors due to these effects. As a consequence, chip designers are forced to account for these effects by applying unnecessary guard-bands to their design, typically in the order of 30% to 40%, therefore negatively impacting the performance of their design, while assuming higher risk with their project.
The incomplete accounting of the physics of thermal effects in the design methodology is costly both in terms of failed parts and in terms of over guard-banding of the design. An analogy can be drawn with the physics of cross-talk and its effect on design verification where the results of the timing analysis and functionality were incomplete without accounting for the cross talk. In today's design the power dissipation estimates are incomplete without accounting for leakage of power. However, unlike cross-talk where linear scaling of the Miller capacitance can be used to guard-band its effects, in the case of leakage power the guard-banding would be exponential.
Thermal IntegrityT techniques can be applied as early as any power estimation and location of the power sources is possible in the design flow to manage the thermal effects. A range of methods employing thermal-equalizationT and temperature-aware-leakage-optimizationT can be used at all points in today's physical synthesis and layout tools to ensure convergence of the performance and reliability constraints, taking into account the electro-thermal effects on the physical design together with the package characteristics.
Dr. Rajit Chandra,
Gradient Design Automation
| | Article | | 09/21/05 | |
| | Cross-talk Timing Fix Flow with CeltIC and PrimeTime
It is highly desired to use a single timing engine in a whole design process in order to guarantee fast timing closure. At National, CeltIC is used for cross-talk analysis sign-off, and PrimeTime for timing verification. Our experience shows that it may be better off to turn off CeltIC timing engine when PrimeTime is used for timing verification. But this strategy may cause another problem: when there are any cross-talk caused timing violations, CeltIC may fail to pick up proper nets to repair. This is because the nets with biggest cross-talk caused delay/speedup are not necessarily the best candidates to repair since they may not be in the critical paths at all.
Without its internal timing engine turned on, CeltIC does not have the knowledge about which nets are part of critical paths, therefore is unable to determine which nets are the best candidates to repair. This paper will describe an internal developed program which is capable of parsing multiple input files and generating a TCL script with potential best candidate nets for noise analysis. With this TCL script, CeltIC will be able to generate proper ECO (Engineering Change Operation) script for the router to fix the timing problems. With CeltIC generated incremental SDF (Standard Delay Format) file, PrimeTime will have all the information necessary to determine which nets are the best candidates to repair: they are in the critical paths with timing violations, and have incremental delay/speedup big enough to cause the problem. In the PrimeTime timing report, instance pin names are used to specify paths. To convert instance pin-to-pin paths to net names, original parasitic net list, typically in the SPEF (Standard Parasitic Exchange Format) format, used for timing and cross-talk analysis need to be referenced. The paper will describe all the details of how to determine which nets to be picked up for CeltIC to do further noise analysis and generate the timing repair ECO script. Both CeltIC and PrimeTime are widely used in the industry for cross-talk noise analysis and timing verification, respectively. This paper will provide the participants with an effective method to deal with the cross-talk timing violation fixes, and share National's experience with Cadence tool users community.
Without the automation provided by the program, it will be very tedious and time consuming, sometimes even impossible, to manually pick up proper candidate nets and to feed them to CeltIC for further noise analysis and repair ECO script generation. Two product designs with 130nm technology showed that our approach was effective and efficient and could reduce the number of iterations a lot and improve productivity greatly.
Wei-Si Jiang,
National Semiconductor
| | Article | | 09/15/05 | |
| | Characterizing Digital Interconnect for A "Big A, Little D", Mixed-Signal Design
When you have a digital block embedded within a larger analog block, you usually have it characterized during it's creation using digital tools. However, when the timing is critical it is necessary to have the timing affects of the routing within the mixed-signal block of the routes to and from the digital block and the boundary of the mixed-signal block. This paper will discuss a methodology using Assura 3.1 to extract selected nets, generating Standard Parasitic Extended Format (SPEF) files for those nets, and then merging it with the model for the digital block. The result gives the capability to do a full timing analysis of the digital block and it's interconnected. Examples of this methodology utilizing Texas Instrument's 130 and 90 nanometer technologies will be shown.
James Giddings,
Texas Instruments
| | Article | | 09/15/05 | |
| | SoC Physical Design Methodology Using Partition-based Integration on Complex 90nm Set Top Box Device
This paper, presented at the SAME conference in August, 2005, discusses evolutions of SoC physical design methodology from former IP-based integration to recent partition-based integration, and describes the methodology used to implement a complex set top box design in 90nm process.
Francois Rémond ,
ST Microelectronics, France
Patrick Bougant,
ST Microelectronics, France
Thad McCracken,
Cadence Design Systems
Paolo Pezzati,
Cadence Design Systems, France
| | Article | | 06/28/05 | |
| | Optimization of Yield Vs. Performance Variability
The RISC and multimedia business unit within Toshiba America is responsible for development of application specific RISC microprocessor based standard products. Cadence interviewed Shardul Kazi, VP of this Business unit, about the design challenges they face in their tapeouts.
Shardul Kazi,
Toshiba America Electronic Component
| | Interview | | 06/01/05 | |
| | Techniques for reducing signal-integrity pessimism
This article discusses Signal Integrity analysis solutions such as noise-glitch false-failure filtering, advanced glitch filtering, SI-on-delay pessimism reduction, timing window iteration, SI slew propagation, and alignment of attackers.
Rahul Deokar,
Cadence Design Systems
| | Article | | 01/24/05 | |
| | Alternative Flip Chip Methodologies in First Encounter
This paper walks you through the methodology for placing and routing I/O bumps and driver cells, and compares several methods of defining the bumps. It discusses how, in addition to using bump instances or LEF "tiles" containing groups of bumps, bumps can now be defined as DEF PINS, which gives users greater flexibility.
Kevin Kelley,
Cadence Design Systems
| | Technical Paper | | 09/28/04 | |
| | Effect of Grounded vs. Floating fill Metal on Parasitic Capacitance
The goal of metal-fill patterning is to meet the dielectric thickness variation spec for your foundry's lithography requirements, while minimizing added interconnect capacitance. This paper will examine how fill metal affects parasitics, and whether grounded fill has any advantage over floating fill, if all other factors remain equal.
Kevin Kelley,
Cadence Design Systems
| | Technical Paper | | 09/28/04 | |
| | Delay Calculation Meets the Nanometer Era
Discusses SignalStorm NDC, a delay calculator for nanometer designs that boosts speed by up to 5x, and uses computing resources efficiently, consuming up to 80% less memory than traditional tools.
Rahul Deokar,
Cadence Design Systems
| | Technical Paper | | 01/01/04 | |
| | Routing Requirements for the Nanometer Era
In the nanometer era the key to fast, predictable design closure is early, accurate access to wires. This paper discusses why wires are so important and how you can obtain the best wires.
Dave Desharnais,
Cadence Design Systems
| | Technical Paper | | 01/01/04 | |
| | Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning
Capturing the designer’s intent during floorplanning plays a critical role to improve design productivity of systems-on-chip (SoC). This paper presents a design technique which helps manage changes very late in the design process caused by the concurrent implementation of blocks in a hierarchical layout.
We developed a floorplan description language and associated a methodology to capture the actual designer’s intent for block placement, soft macro shaping, JTAG cell placement, power grid and power rings design.
This approach has successfully been applied on a complex SoC and IP block implementation. It has demonstrated a reduction from one day to few minutes for a floorplan iteration, crucial in a concurrent design environment where asynchronous changes in the blocks require to constantly revisit the top level layout and vice versa.
Herve Menager,
Philips Semiconductors, San Jose
| | Article | | 11/13/03 | |
| | Nanometer Sign-off—From Design to Manufacturing
Discusses a nanometer sign-off flow comprising silicon-validated analysis engines that account for the interactions of multiple noise sources such as crosstalk and IR drop.
Igor Keller,
Cadence Design Systems
| | Technical Paper | | 03/01/03 | |
| | Signal Integrity Closure
With the increasing number of potential SI problems in the nanometer era, designers must tackle SI effects as the design is implemented. This paper discusses an integrated approach to SI closure.
Shiva Raja,
Cadence Design Systems
| | Technical Paper | | 03/01/03 | |
| | Physical Prototyping—Key to Nanometer SoC Design
Describes a design methodology for the implementation of multimillion-gate, nanometer system-on-a-chip (SOC) designs.
Kit Lam Cheong,
Cadence Design Systems
| | Technical Paper | | 09/01/02 | |
| | Noise-aware Timing Analysis
Shows how noise effects can easily change timing results by over 20% and discusses an effective solution for the problem of noise-aware timing closure.
Venkat Thanvantri,
Cadence Design Systems
| | Technical Paper | | 06/01/01 | |
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