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 | |  | | | Cadence, Altera, Elpida DDR2 Memory Design-in IP
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| This design-in IP includes a methodology for designing system-level DDR2 memory interfaces that leverages IP from Altera Corporation, Elpida Memory, Inc. and Cadence Design Systems. The IP Portfolio in Japanese language offers a reference design from Altera with a Stratix II memory controller that talks to Elpida DDR2 SDRAM. It includes IO buffer models, package models for the DDR2 memory from Micron, several topologies for all the signals in the DDR2 interface for DIMMs as well as on board memory. The design-in IP accelerates the time to design interfaces that use DDR2 memory interfaces. The methodology can be applied to other high-speed source synchronous signals as well. Download the DDR2 memory Design-in IP now. Download the DDR2 memory Design-in IP now.
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| | Cadence, Altera, Elpida DDR2 Memory Design-in IP »
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