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 | |  | | | Rambus design-in kit for PCI Express RaSer PHY
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| This silicon design-in kit includes all you need to perform serial link simulation with Rambus PCI Express RaSer PHY technology at either end of your PCI Express link. Included is a behavioral MacroModel for a RaSer PHY that correlates to transistor-level models but runs hundreds of times faster. The PCI Express design chain is created to help you implement the PCI Express architecture in systems design. Cadence has brought together several PCI Express design-in IP from Cadence partners to help you optimize the use of this PCI Express design chain. The partner design-in IP include various simulation models and circuits, PCB constraints and layout helps, and other items targeted for the Allegro environment. Register and download your PCI Express Design-in IP Portfolio
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| | Rambus design-in kit for PCI Express RaSer PHY »
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