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Xilinx RocketIO Design-in kit Discuss this content or topic in the Silicon-package-board forums Description The Virtex II Pro 3Gb/s RocketIO Design-in Kit for Allegro PCB SI, an electronic blueprint for simulating and implementing Virtex-II Pro RocketIO transceivers in a system, allows you to develop optimal constraints for your PCB systems. These constraints then drive PCB floorplanning, routing, and verification processes. The kit comes in two sections, part from Cadence and part from Xilinx. Download, the Cadence portion now. The Xilinx portion, available with a Xilinx click license can be downloaded from the Xilinx Download Center. Select "Spice Models" for Update Type and "Virtex-II Pro" for Device Family. After submitting this request, enter your Xilinx ID. The Allegro PCB SI kit is found in the file, sis_kit_v2p.zip(8.66 MB), Release Date: 10/7/04 Description: Virtex-II Pro Signal Integrity Simulation Kit v3.7. The combined kit includes proven and correlated models, PCB constraints, topologies, scripts, and utilities that will help you integrate Rocket I/O Transceivers into your high-speed Virtex-II Pro™ designs . This zip file contains additional information about using this design-in kit. Files Xilinx RocketIO Design-in kit » Ratings   This content has not yet been rated by other users   Comments