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| Most analog circuits are susceptible to mismatch. One source of the mismatch is the misalignment of layers on a wafer, e.g. between poly mask and active layers. For two MOS transistors placed as mirrored devices in the layout, if the poly misaligns perpendicular to the gate endcaps, the source and drains areas become unequal. These misalignments are acceptable for digital circuits, but can cause yield problems in analog circuits. Other sources of mismatch can be misalignment between Metal-1 and Poly, or between Metal-2 and Metal-1. Creating a layout that is insensitive to this form of mismatch is important to good yield. Existing physical verification flows do not catch mismatch errors due to mask misalignment. There are five possible combinations of any two layers, center, up, down, left and right. In this paper, winner of the People's Choice award at CDNlive! Silicon Valley 2006, a flow will be presented using Assura RCX to simulate the mask misalignments using the geomShift command. A script creates each of the desired layer pair misalignments followed by parasitic capacitance extraction to generate a spice netlist. A PERL script then looks at each node of each run and compares the base capacitance value for the net with the shifted mask capacitance. If the values differ, that node is marked as having a mask alignment sensitivity.
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| | A Method of Identifying Analog Cell Mismatch Issues Caused by Photo Mask Misalignment »
A Method of Identifying Analog Cell Mismatch Issues Caused by Photo Mask Misalignment, PowerPoint Presentation »
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About the author
David Schwan has over 25 years experience in CAD and layout. He is currently the Manager of CAD and Layout at Micro Linear, and is responsible for all EDA tools used at Micro Linear. He is the author of numerous papers covering CAD methodology, IP, IC Layout, and RF Design. He is an active member of the FSA Mixed Signal/RF subcommittee, and is an active participant in the FSA/VSIA Hard IP (HIP) quality metric. |
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