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| Cadence Abstract Generator (AG) is widely used by designers to generate abstracts from detailed layouts in order to facilitate Place and Route flows. AG can generate abstracts in OpenAccess 2.2 and Lib Exchange Format (LEF). AG has been revamped in latest IC6.1.0 release to address design challenges at lower process technologies as well as for tighter integration with the Virtuoso and SoC Encounter design environment. The presentation showcases advanced blockage models, metal density calculation and new antenna models for 65/90nm technologies. Readers will be able to appreciate how these new features help resolve critical issues at these process nodes. The presentationl highlights the new AG GUI, fully integrated in Virtuoso environment. The presentation also provides examples of using AG from SoC Encounter environment natively. Readers will learn how to create abstracts with a single click and set some basic parameters to fine tune the abstract generation process. Custom block authors and library developers as well as digital designers will appreciate the ability to generate abstracts within their familiar environments. The presentation presents many other features like faster extraction for block power grids, supply and ground sensitivity for multiple supply and multiple voltage (MSMV) designs, support for gate array style cells and minimum area checks for pins. The paper also demonstrates greater flexibility in reading logical information using NCVerilog based verilog import. Readrs will also learn how to provide pin information using the Synopsys Liberty format.
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| | Generating Abstracts for 65/90nm designs using IC6.1.0 »
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About the author
Anshul is a technical leader in the custom IC product validation group at Cadence, India.
Anshul has 7 years of industry experience and has worked with various custom design tools
from Cadence namely Abstract Generator, Virtuoso Preview/Floorplanner, Stream translators etc.
He graduated from Delhi University with a Bachelors degree in Electronics and Communication
Engineering in the year 2000.
About the author
Sanjib Ghosh received his MS on VLSI Design and Cad from the "Indian Institute of Technology - Delhi" . His area of interest and thesis is on "Numerical Optimization Algorithm". Sanjib has worked with Cadence for the past seven years, mainly in physical design, and is currently a Member of the Consulting Staff. |
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