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| Formal verification in general and logic equivalent checking in particular are problems that are hard to solve. However, most of the hardware logic doesn't fall in the worst case category and therefore can be computed by logic equivalence checking tools like Cadence Conformal (LEC). In this presentation we explore how to use the Cadence Conformal LEC tool capabilities to verify different types of designs. In particular, we focus on the Conformal Ultra capability for verifying complex data-path synthesis and layout. We will use it together with the set effort "complete" command, in order to force the Cadence Conformal LEC to compare all the aborted state points. The design we present is a 1 Gigabit Ethernet chip with around 10 million standard cells. At first look we thought that we would need to use the divide and conquer technique and split the big design into smaller blocks in order to complete the verification. To our surprise, using the Conformal Ultra together with the effort "complete" we managed to verify the entire design in one flat run. In this presentation we discuss when to use the different Cadence Conformal LEC capabilities and what benefits they provide. When to use the Conformal Ultra and when not? Why you need to use the effort complete wisely? The following learnings are based on using the Cadence Conformal LEC on different types of designs at Intel. This kind of information can provide a significant saving of time and increase the user productivity. We wrap up by presenting additional tips of accelerating the design flow using the Cadence Conformal LEC.
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| | Cadence Conformal LEC - The Intel Experience »
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About the author
Itai Yarom is the design and verification technical lead of LAN Access Division (LAD). Itai was a key player for improving LAD and Intel design and verification flows by driving new technologies, including formal equivalence checking, formal property verification, assertion based verification, SystemVerilog, DFT (Design-For-Test) and DFD (Design-For-Debug). Itai is the chair of the Intel SystemC User Group (ISCUG) and the Intel ESL Summit. Itai is a member of the Conference Advisory Board (CAB) of the functional verification track in the Mentor U2U conference and the chair of the advanced synthesis and verification methodologies in the IEEE International Conference on Electronics, Circuit and Systems (ICECS). Itai was the author of more than 20 papers and has several patents. Itai is the instructor of the advance VLSI seminar and exposure to the industry courses in the Hebrew University. Itai had joined Intel at 1998. Itai is a researcher in the center of rationality in the Hebrew University at Jerusalem, where he had received his MSc (2001) and BSc (1998) in computer science. |
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