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Methods to Improve Verification Quality on the Module Level Discuss this content or topic in the Functional Verification forums Description This presentation, winner of the Best Paper Award in Functional Verification at CDNLive! EMEA, discusses the challenge of obtaining high quality verification on SoC projects with many new or revised modules. To achieve this, Siemens AG Automation and Drives uses a consequent Plan-to-Closure Methodology. This allows smart combinations of several verification methodologies, while high-quality coverage-driven verification remains the most important task. Files Methods to Improve Verification Quality on the Module Level » About the author Since 1999 Markus Gross has been part of the ASIC design team of Siemens Automation and Drives in Erlangen, starting with logic design and synthesis. Marcus switched to verification when his group began using Specman Elite and e in 2002 and has written several verification environments since. In his teams recent projects Markus was responsible for developing new verification processes and strategies as well as supporting new verification engineers. Ratings   This content has been rated 4 out of 5 by other users   Comments