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 | |  |  | | | | Challenges for Designing with DDR2
An interview with Sogo Hsu, Ph.D.
Foxconn Taiwan | |
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With DDR2 design, what kind of challenges do you face when dealing with timing?
In DDR2 design, the major bottleneck is compliance with different memory module vendors. In JEDEC spec. (JESD79-2A), input slew rate tables were introduced in DDR2 to allow more accurate estimation of setup and hold time margin. At DDR2-667 and DDR2-800, tens of picoseconds become significant when closing the timing budget. Our challenges are to ensure the design can be compliance with several memory module products which have different loading and routing. From simulation point of view, the challenges are
- Automatic parametric solution space sweeping of topology, drivers, PCB parameter and receivers.
- Automatic random patterns generation and identification of failure if has.
- Automatic sweeping of voltage. (Integration with power integrity)
- Automatic source synchronous timing calculation, both for read/write cycle and light/heavy loading
With DDR2 design, what kind of challenges do you face when dealing with Signal Integrity?
Although the signal speed of DDR2 is not as high as PCI-Express. However, the SI issue of DDR2 is more difficult than PCI-E. PCI-E is in serial and DDR2 is in parallel instead. The reflection from stub and crosstalk noise will be more serious as the signal speed of parallel bus going high.
With DDR2 design, what kind of challenges do you face when dealing with Power Integrity?
During read/write operation, the high speed buses will demand on large current flow and result in power integrity issue. However, the syndrom did not present along. It often represented in setup and hold time failure. I prefer to combine signal integrity, power integrity and timing analysis to obtain a clear picture of root cause of failure.
What difficulty to you have with models for DDR2 design?
The challenge encounter with IBIS was modeling of On Die Termination circuit. There are different solutions for different vendors. Many questions were raised about the best way to accurately represent the On Die Termination circuit characteristics. Meanwhile, we have to verify the accuracy and availability of models in advance. JEDEC has defined the required characteristics of IO buffer. In my opinion, a default model which is parameterized is welcome for verification.
What about ODT & DDR2 ?
On-die termination (ODT): ODT is a key part for improving signal integrity while we performing DDR2 design, this hardware function can be implemented automatically by ODT signals in DDR2. But, in simulation level, ODT turn on/off should be judged by SI engineer and implemented by manually setting in the IBIS model selection. Different DIMM slots population need different ODT combinations. There exist lots of complexities and causes error results by ignorances. If there are some guidelines in the DDR2 design kit and lead SI engineer choose a right combination for ODT in their design case, that will help engineer doing right thing in first time and prevent errors from ignorance.
What about slew rate de-rating and frequency dependent timing models & DDR2 ?
Slew rate derating and frequency dependent timing: Because of intrinsic delay of input receiver will heavily depend on input waveform, in simulation level, if we want perform a reasonable timing margin analysis (setup/hold time margin), we have to add some derating value on the input waveform measurement in simulation level by referencing derating table offered by DRAM datasheet. The difficulty is how to make mapping between derating value in table and slope measurement in simulation. The slope measurement will depend on the linearity of input waveform's rising/falling edge, once you get the slope value, interpolation maybe perform if you want get proper derating value in the referece table. If all the process can be implemented by automatically, that will save more time to do simulation.
What about Populations & DDR2 ?
Populations: To build in different topologies for DDR2 design and different DRAM models for user to choose, that will be helpful for user to specify topology they want. The compatibility issue always is annoyances on PC makers, how to build reasonable corners matrix to coverage wide variation in design is a key concern. But in Cadence current solution, SSN/SSO analysis could not include correct power/ground plane model to predict correct signal noise and timing margin is a drawback. In current market, Cadence still is a most probable solution to do such kind of complex design simulation.
What about ISI & DDR2 ?
Inter-Symbol Interference (ISI): ISI is heavily relying on signal bit pattern, how to define a worst bit pattern is the most important thing. We don't know if DRAM vendor have defined such bit pattern (like memory test) to criterion/verify their DRAM quality. If such defined pattern is qualified or not to get worst ISI is our key concern. In current solution, each PC makers may have its own experience to produce worst bit pattern; but we still hope there is a standard reference. By the way, ISI caused by input/output buffer characteristic will not be revealed from IBIS model. The only way to check ISI from buffer is by use of HSPICE model in transistor level.
What about PVT & DDR2 ?
Process, Voltage, and Temperature (PVT): It is hard to take process and temperature into consideration but voltage maybe. Voltage variation will lead to variation in noise margin and signal integrity. How to take voltage variation into current IBIS model is a key point.
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About the author
Sogo Hsu is an electrical engineering leader at Taipei Design Center, Foxconn Inc., where he is responsible for the development and technical support of high speed digital product design by simulation strategy. He received a Ph.D. from National Taiwan University, Taipei, Taiwan in 1995, and continued as an associated professor until 2001. He joined Foxconn in 2002 to focus on electrical simulation methodology. He is interested in topics including Multi-gigabit link interface design, high speed digital design flow automation, signal/power integrity simulation, Timing verification, RF/microwave theory, and interconnection modeling for packaging . |
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