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| SigXplorer Batch Mode Simulations
SigXplorer is a topology exploration tool that allows users to explore solution spaces and simulate advanced buses. The environment is highly interactive, meaning that an operator is often required to perform some basic tasks that can be automated. This application note shows how some of those tasks can be automated in order to run the tool in batch mode. The application note will describe how you can simulate any number of topology files using command line scripts. Examples will be given for Windows and Unix.
Lance Wang,
Cadence Design Systems
| | Application Note | | 06/01/06 | |
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| Effective Modeling and Analysis of EMI Effects on Printed Circuit Boards
With the increasing of signal frequencies in high speed systems, it is critical for electronic products to pass EMI test before going into the market. Failure in the EMI test can result in high product cost and long development cycle, or losing marketing opportunity. This paper, presented at DesignCon 2006, first describes what procedure is effective and efficient to prevent EMI problems for a product that includes high frequency parts. It then presents the methods to predict common mode radiation and power ground plane resonance based on circuit analysis and 2-dimensional transmission line theories. The methods are also verified by full wave electromagnetic field analysis, plane model simulation, and measurements.
Kun Zhang,
Huawei Technologies Co, ltd.
Zhen Mu,
Cadence Design Systems
| | Technical paper | | 03/16/06 | |
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| Solving Signal Integrity and EMI Problems Early
Kun Zhang and his team at Huawei believe preventing problems according to proven solutions are much more important than correcting problems when they are detected in the end products. In this interview Kun Zhang discusses strategies to prevent EMI problems.
An interview with Kun Zhang,
Huawei Technologies Co.
| | Interview | | 06/01/05 | |
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| Resolving EMI Problems with Good Power Delivery Strategy
This paper discusses the relationship between EMI and Power Integrity in high-speed PCB design. It proposes and investigates design methods to suppress power ground noise by including RC termination at the PCB edge and by localized decoupling. Evaluation boards are designed and manufactured to verify these methods.
Kun Zhang,
Huawei Technologies Co.
Zhen Mu,
Cadence Design Systems
Qingshan Quan,
Huawei Technologies Co.
Xiangzhong Jiang,
Huawei Technologies Co.
| | Technical Paper | | 06/01/05 | |
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| High Performance Backplane Trends
Chris Heard of Teradyne Corporation has contributed a technical paper, “High Performance Package Trends Driving BackDrill File Generation Using Cadence Allegro”. We interviewed Chris about increasing routing channels for high performance backplane.
An interview with Christopher Heard,
Teradyne Corporation
| | Interview | | 05/01/05 | |
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| Using Hspice as the Simulation Engine Under Allegro PCB SI
Contains all the information you need to enable, test,
and use the aSI-Hspice interface. In addition to the embedded simulation
engines in Allegro PCB SI (aSI), you can also direct your PCB simulations to
Hspice. Once enabled, the interface allows you to use encrypted Hspice models
within the familiar aSI GUIs. As such, Hspice models can plug-and-play with
powerful aSI features such as integrated PCB field solvers, automated sweeping,
multi-board simulation, Custom Measurements, and Channel Analysis.
| | How to Kit | | 09/01/04 | |
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| Best Practices for High-speed Digital PCB Design
Presented at the 2004 ICU Conference by Jeurgen Flamm this paper presents an overview of new technology presented with the launch of the Cadence Allegro System Interconnect platform. The paper presents the challenges inherent in today’s fast-paced electronic design environment, and then presents a design and verification flow to increase engineer productivity.
Juergen Flamm,
Cadence Design Systems
| | Technical Paper | | 09/01/04 | |
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| How to Choose and Place Decoupling Capacitors to Reduce the Cost of Electronic Products
Provides a solution for choosing decoupling capacitors
early in the design process. The method described in this paper shows how a
more effective decoupling can be achieved with fewer decoupling capacitors
using a real design example.
Kun Zhang,
Huawei Technologies Co, ltd.
Zhen Mu,
Cadence Design Systems
Heiko Dudek,
Cadence Design Systems, Germany
| | Technical paper | | 08/01/04 | |
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| Investigating Via and Discrete Capacitor Effects Using Power IntegrityDesign Tools and Measurement Results
Discusses the effects of via density on power delivery
systems designed for high-speed PCBs. This paper investigates and discusses the
effects of via density on power delivery systems designed for high-speed PCBs,
the decoupling effect of discrete capacitors, and the precision of simulations
conducted with the Allegro PCB PI option 610 (SPECCTRAQuest SQPI) power plane
module (determined by correlating simulation results with measurements). For
the purpose of this experiment, evaluation boards were specially designed and
manufactured. Results of frequency responses between VNA measurements and
Allegro PCB PI simulations were then compared.
Kun Zhang,
Huawei Technologies Co, ltd.
Zhen Mu,
Cadence Design Systems
Heiko Dudek,
Cadence Design Systems, Germany
| | Technical paper | | 04/01/04 | |
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| Meeting EMI Requirements in High Speed Board Design with Allegro PCB SI
Discusses rule checking in the high-speed design flow
Even though Signal Integrity (SI) is becoming more and more critical in today's
high-speed PCB designs, electromagnetic interference (EMI) tests remain the
only standard for an electronics product go to market. This paper discusses the
tasks of enforcing EMI rules and the necessity of integrating automatic EMI
into the design.
Zhen Mu,
Cadence Design Systems
| | Technical Paper | | 03/01/04 | |
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| Calculating Impedance in Allegro PCB SI
Allegro PCB SI uses an electromagnetic field solver for transmission line impedance extraction. Given the board stackup geometry, the field solver extracts the frequency dependent inductance matrix, resistance matrix, conductance matrix and capacitance. This FAQ discusses how Allegro PCB SI extracts transmission line characteristic impedance.
| | FAQ | | 02/12/04 | |
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| Setting Environment Variables for Allegro PCBSI Simulations
Describes how to set environment variables for Allegro
PCB SI simulations. There are several different ways to set environment
variables in the Allegro platform environment. Simulation-related variables are
best handled using a local “env” file which is read by Allegro PCB SI at
start-up. This app note describes the recommended procedure for doing this.
Ken Willis,
Cadence Design Systems
| | Application Note | | 11/01/03 | |
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| Using Allegro PCBSI to Analyze a Board's Power Delivery System from Power Source to Die Pad
Introduces options to perform post-layout analysis of a power
delivery path from power source to the chip supply rails. The presentation
shows a three-step approach utilizing Allegro PCB SI-PI and Allegro PCB SI-SSN
options and features of the tool, briefly touching on capabilities that enable
the design engineer to perform comprehensive types of simulations. The paper
gives more detail on the three-step approach found in the presentation.
Juergen Flamm,
Cadence Design Systems
| | Application Note | | 09/01/03 | |
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| Ensuring Signal Integrity in a Memory Subsystem
Allegro PCB SI simulations enabled first-time routing
success routing for memory modules. Aggie Cabral and his team were charged with
designing a new custom memory module for Celestica's Memory Development Group,
and linking it with the customer's motherboard design. They knew they were
going to have to solve some challenging Signal Integrity issues in order to
"get it right the first time."
Aggie Cabral,
Celestica
| | Technical paper | | 06/01/03 | |
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| Addressing Crosstalk in High-speed Designs using Allegro PCBSI
Describes an approach for addressing crosstalk in
high-speed digital designs using Allegro PCB Si There is an arsenal of
functionality in Allegro PCB SI to address crosstalk, including on-line Design
Rule Checks (DRCs) and full coupled-line time domain simulations. This app note
describes one strategy in which these capabilities can be deployed to help
minimize crosstalk.
Ken Willis,
Cadence Design Systems
| | Application Note | | 03/01/03 | |
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| Anatomy of a Signal Integrity Failure
Presents a case study examining a Signal Integrity
failure on a 133 MHzGTL bus. The race to develop new multi-Gb per second
interfaces has created a drag effect that is sweeping seemingly nondescript
buses into the critical path. Both new and experienced Signal Integrity
engineers will benefit from Greg's experience.
Greg Edlund,
IBM Engineering and Technology Services Division
| | Technical Paper | | 02/01/03 | |
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| Inside Differential Signals
Describes a differential signal, how to assign
differential drivers and receivers, routing and terminating trace pairs
Lynne Green,
Green Streak Programs
| | Technical Paper | | 12/01/01 | |
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| Inside Simulation and Modeling
Discusses simulation and modeling to ensure Signal Integrity and EMI. Covers the basics of simulation, such as using models for simulation, modeling standards, and the relationship between Signal Integrity and EMI simulation.
Lynne Green,
Green Streak Programs
| | Technical Paper | | 10/01/01 | |
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| Simulation and Modeling for Signal Integrity and EMC
An introduction to SI simulation and the relationship
between the time-domain (SI) and frequency-domain (EMC) views of a digital
signal. Presented by Dr. Lynne Green as part of the EMCS T-10 Workshop at the
IEEE 2001 International EMC Symposium, Montreal, Canada, the paper provides an
introduction to SI simulation and the relationship between the time-domain (SI)
and frequency-domain (EMC) views of a digital signal. Discusses differential
models, validation methodology, and high-speed interconnect models.
Lynne Green,
Green Streak Programs
| | Technical Paper | | 08/01/01 | |
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| Getting on Board with Optics
Explores why and when to use fiber optics as well as
similarities and differences between optic interconnects and electrical
interconnects.
Lynne Green,
Green Streak Programs
| | Technical Paper | | 02/01/01 | |
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| Using Custom Measurements for Source Synchronous Applications
Shows the basics of the source synchronous application
When you first look at Custom Measurements you may not realize that you can
write one measurement that will be taken in repetitively in every cycle during
the simulation.
Donald Telian
| | How to Kit | | 08/01/00 | |
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| Behavioral Receiver Modeling
The who, why, what, how and where of behavioral receiver
modeling Using the Allegro PCB SI flexible MacroModeling language you can model
just about any behavior you'd like to test or imitate. Clever users have built
MacroModels to model complex IOCells like complete differential IOs (correctly
modeling input to output behaviors, including delays) and dynamically
compensated buffers.
Donald Telian
| | Technical Paper | | 01/15/00 | |
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| Using SPICE-level Connector Models in Allegro PCB SI
How to and examples of using SPICE-level connector models
in Allegro PCB SI Using these examples, you can build just about anything. And
note that the Allegro PCB SI modeling language allows you to specify pin
numbers—as "x", "x-1", "x-2", etc.—to help you model just a section of a
connector. This is consistent with the models offered by most connector
vendors. Both SPICE language and RLGC model formats are supported. If you are
working with RLGC data, make sure you look at the examples in your install
(/share/pcb/signal/cds_packages.dml) to see the various matrix formats
supported.
Donald Telian
| | How to Kit | | 09/15/99 | |
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| IBIS Made EZ
Simplifies the IBIS specifications If you're new to IBIS,
and find the size of the specification rather daunting, this should make the
topic more accessible.
Donald Telian
| | Technical Paper | | 07/01/97 | |
|
| Signal Integrity Engineering in High-speed Digital System
Addresses the 7 roles the Signal Integrity Engineer must
play at various stages of the hardware development cycle This paper, presented
at DesignCon 1997 by Donald Telian, identifies the role of the “Signal
Integrity” engineer and discusses the correct application of SI theory, tools
and models from successful real life execution.
Donald Telian
| | Technical Paper | | 02/01/97 | |
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