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| Effectively Using SKILL in the Allegro PCB/MCM/SiP Environment
Skill is a very powerful feature in Allegro physical layout editors for PCB/MCM or SiP. The user can customize, or add new functionalities at their own environment on top of a Cadence release. This is an interpreted language with some very powerful language features. In addition to language features, Allegro provides a rich set of interfaces which are optimized for a particular class of operations. Users can get better result in terms of performance, using less code if these interfaces are used in their programming. This presentation highlights some programming tips on how the user can write Skill code effectively using the language features as well as some of the available Allegro Skill interfaces. Some examples highlighting how the user can write better Skill code, are discussed in the presentation. This presentation also describes how the user can package their Skill code and integrate with an existing Cadence release at the site or user level.
Utpal Bhattacharya,
Cadence Design Systems
Frank Farmar,
Cadence Design Systems
| | Article | | 10/16/06 | |
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| An Advanced Fabrication Array Utility
Array (or panel) use is common throughout PCB assembly plants. Arrays provide standard profiles that assembly plants can handle more easily than single-up boards and provide cost efficiencies due to being able to place more parts in a single operation. Many companies leave the task of putting several designs in an array to their CAM department or fabrication house. However, with increasingly complex board outlines and requirements to avoid stresses on surface mount devices, in-house design of the arrays is often required. Tait Electronics has developed an Allegro Skill utility to design arrays. This utility makes use of the ODB++ output format. This means that board data can be stepped and repeated without creating massive data files and board changes do not require multiple copy and paste actions. This session will include a discussion about the advantages of this method of array design and a demonstration of the tool in action. Tait PCB designers took up to two days to design arrays when using third party tools to design arrays. A typical array design is now done in about two hours. Re-use of array designs makes this even more efficient.
Dave Elder,
Tait Electronics
| | Technical Paper | | 09/18/06 | |
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| DRC Manager: Third Generation Tool to Handle DRCs
As usage of the Allegro constraints system increases, so does the need for automation to handle DRC violations. This discussion focuses on the SKILL features and concepts used in development of a third generation tool for managing both Allegro and External DRC violations. There have been SKILL tools in the past for the orderly viewing of DRCs, but the Intel developed DRC Manager goes a step further in organizing, prioritizing, disposition and reporting DRCs. Other solutions have often been limited by the volatility of DRC dbids, however the DRC Manager makes extensive use of attachments in the design and a reconciliation algorithm to avoid this nuisance. Along with attachments, many other advanced SKILL techniques will be discussed that enabled the development of customizable and resizable UIs, multiple selection DRC lists, multi-filter capability, text searching and tool configuration settings.
Much time has also been spent considering various DRC Management usage models and requirements from an Allegro user perspective. By establishing a few tool guidelines External DRCs generated by a company's validation routines can also be managed in the same manner as Allegro DRCS. In DRC Manager, DRCs may be selected by various criteria which can make an unruly number of DRCs more manageable. Along with typical category filtering, a text search allows for more unique analysis such as X-Y location, net name, violation context (e.g. Via related.etc), often helping the user to find that one pesky violation. A Disposition feature allows placing the DRCs into categories of Fixed, Needs Fixing, Deleting, or Waiving. Custom matching algorithms allow for this Disposition to be persistent as long as the DRC exists. User comments may also be associated with DRC violations. This type of data is extremely useful during design reviews and when included in DRC violation reports. Along with already mentioned features, many more concepts will be presented including: user defined priorities, attachments and user settings, export/import of data and settings, command line processing and controlling the visibility of DRCs.
Effective DRC Management enables noticeable efficiency gains in the final stages of a design cycle and prevents potential design escapes. Many DRC Management techniques used today are very user dependent and require more manual and repetitive effort than should be necessary.
The actual software for DRC Manager will not be shared. The primary SKILL concepts, use model considerations, and example cases will be explained to a level of detail that allows for recreation of the software capabilities.
Damon Cecil,
Intel Corporation
| | Technical Paper | | 09/12/05 | |
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| Effectively Using SKILL in the Allegro PCB Environment
Addresses several topics about developing Allegro Board
or Package commands using the SKILL language
Frank Farmar,
Cadence Design Systems
| | Technical Paper | | 09/01/04 | |
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| OOD Shapes
This skill code is tested with Allegro Release 15.1
Ron Guthrie,
Cadence Design Systems
| | SKILL Routine | | 03/01/04 | |
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| Find dlines
Created a form driven interface. The form will display all the dangling clines and dangling lines.
Larry Bowman,
Cadence Design Systems
| | SKILL Routine | | 03/01/04 | |
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| Replace via padstack by window
The "replace via" command allows the user to select
multiple vias through a find by window. If more than one via padstack name is
found, the command will prompt the user for which via padstack name they wish
to replace.
| | SKILL Routine | | 10/01/03 | |
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| Find components over, under, equal to a user specified height value
This program finds components over, under or equal to a
user specified value, on the side specified. It also finds the highest
component. Single pick mode lets you pick any symbol in the layout.
Geoff Meek,
Rogers
| | SKILL Routine | | 09/01/03 | |
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| Highlight Padstack
This program makes a list of component pin padstacks /
vias, and a list of drill sizes in the layout. ;The users then picks a name
from either list. ...the padstacks are highlighted.
Geoff Meek,
Rogers
| | SKILL Routine | | 09/01/03 | |
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| The Successful Use of SKILL for Allegro PCB Editor and Allegro Package Designer
Presents an example of a network installation allowing for full control of the SKILL environment by the individual or group responsible for maintenance, plus GUI development and IP protection.
Moody Dreiza,
Amkor Technology, Inc.
| | Technical Paper | | 09/01/03 | |
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| Tcl/Tk and SKILL - A Brief Introduction to GUI Development in Cadence Design Systems PCB Design Environment
This paper provides a brief introduction to GUI development with Tcl/Tk, visualizes the basic methods of how Cadnece IPC Skill functions can communicate with such Tcl/TK applications and how to embed them into your PCB Design Environment.
Andy Kulik,
PTC
| | Technical Paper | | 09/01/03 | |
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| Check Width
This program will flag all connect lines in a user
defined area that do not match a user defined width.
| | SKILL Routine | | 09/01/02 | |
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| Display DRCs in Allegro design
This function will generate a list of DRCs in the current
design, and allow the user to 'walk through' the list to inspect/verify/etc.
User can filter the list of DRCs by layer and/or type.
| | SKILL Routine | | 09/01/02 | |
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| Show Height Text
Copies the 14.x package height_min/max properties to
visible text for display and printing. This program will search for component
height properties attached to place bound shapes. The value of the properties
will be entered as text and placed next to the place bound shape. Users will
then be able to print drawings with the height of the components visible.
Ron Guthrie,
Cadence Design Systems
| | SKILL Routine | | 06/01/01 | |
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| Find and Identify Stubs
This SKILL routine will find and identify "stubs", pieces
of etch on a net that do not terminate on a pin/via/tee on both ends and pieces
of etch that have either both ends terminating on the same shape or one end
terminating on a shape and the other not terminating against a
pin/via/tee.
Chris Walters,
Motorola
| | SKILL Routine | | 04/28/00 | |
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| Allows the User to align Component Package symbols
Allows the user to align component package symbols by
component origin or by component pin 1.Items may be picked by top, bottom or
both. Items may be selected by window, group or tolerance. In selecting by
group or window, the user may specify choice by class.
Edward B. Acheson,
Cadence Design Systems
| | SKILL Routine | | 12/01/93 | |
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