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| | | | | | Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Verification Planning and Management is rapidly becoming accepted as an important technical discipline for advanced designs. There are a number of ways to take advantage of its benefits. Cdnusers talked to Ze'ev Shtadler, Cadence RnD Group Director for Advanced Verification Solutions, about the methodology and how it is used.
Ze'ev Shtadler,
Cadence Design Systems
| | interview | | 03/24/08 | |
| | Parallel and Modular Flows over a Basic Chip Level Environment
Discusses Parallel and Modular flows used in making various products
Shlomi Sperber,
Texas Instruments, Israel
| | Article | | 03/05/08 | |
| | Interview: Coverage-driven Random Verification
Coverage-driven random verification methods, supported in the recent Cadence® Incisive 6.2 software release, are becoming recognized as one of the best ways to verify complex IC designs. To understand how to take advantage of this solution, we talked to Apurva Kalia, VP of R&D for the Incisive product line. For the past year, he has been working on the latest technology advances in the area of coverage driven verification.
Apurva Kalia,
Cadence Design Systems
| | Interview | | 02/07/08 | |
| | By Popular Demand—SystemVerilog Open Verification Methodology
Cadence and Mentor Graphics announced that the new Open Verification Methodology for SystemVerilog is available for download. To understand the relevance of the announcement, we talked to Tom Anderson, Cadence Verification Product Marketing director; Mike Stellfox, Cadence Verification Solutions Architecture team lead; and Erik Panu, Cadence Incisive Plan-to-Closure Methodology and Verification IP Development group director.
Tom Anderson,
Cadence Design Systems
Erik Panu,
Cadence Design Systems
Mike Stellfox,
Cadence Design Systems
| | Interview | | 01/09/08 | |
| | Closing in on Profitability with Leading-Edge Verification Practices
Design and verification engineers use a variety of methods to verify advanced designs and build verification environments. The question is whether there’s a best way to do it, or are there a number of acceptable ways? To answer this question, Cadence® engineers have developed technology that includes best practices and guidelines that close the gap on predictability and profitability for complex SoC and full-chip designs.
This technology—the Incisive® Plan-to-Closure Methodology—is included in Incisive Enterprise Simulator, Design Team Simulator, Specman Elite® Testbench, and Specman ESL solutions. However, not everyone who has the methodology is using it, so cdnusers talked to Cadence design engineers Mike Stellfox and Erik Panu to find out when and how to deploy the new technology.
Erik Panu,
Cadence Design Systems
Mike Stellfox,
Cadence Design Systems
| | Interview | | 12/05/07 | |
| | Verification of Low-Power Designs using CPF
The power wasted by leakage current can no longer be ignored in sub-micron designs. As the size of transistors shrinks, the amount of current due to leakage rises exponentially. In order to minimize the power lost due to leakage, several design techniques have been developed. Functional defects can be introduced if these features designed to reduce power are either specified or implemented incorrectly. The problem is not only being able to detect these functional defects, but also being able to detect them early enough in the design cycle to avoid costly delays. This paper explains how CPF (Common Power Format)-enabled technologies can be used to functionally verify that the features added to save power have not introduced defects. The paper will illustrate how the specification of design features such as power switch-off (PSO), save restore registers (SR), and isolation (ISO) can be verified at an RTL level and the advantages of using a CPF-based flow over an ad-hoc solution.
Noah Bamford,
Freescale Semiconductor
Saji George,
Freescale Semiconductor
Milind Padhye,
Freescale Semiconductor
| | Technical Paper | | 10/23/07 | |
| | Simplifying Vertical Reuse with Specman Elite
To achieve controllability and visibility in the face of increased design complexity, unit-level testbenches are becoming a must; however, schedules often do not allow development of both unit-level and chip-level benches. The solution is vertical reuse, where verification code is used for both the unit and chip levels. This presentation, awarded the People's Choice Award for Functional Verification at CDNLive! Silicon Valley 2007, illustrates techniques that maximize vertical reuse while avoiding significant additional development effort. Examples include reuse of tests at both levels and avoiding the need to develop a top-level checker. These techniques are implemented in the e language, using (but going beyond) eRM features. They have been used on some multi-million gate ASICs, and chip-level testbenches have been ready a few days after unit-level benches are complete.
Mark Strickland,
Cisco Systems
| | Technical Paper | | 10/03/07 | |
| | Translation of an Existing VMM Testbench into URM
Many features built into the SystemVerilog language make it ideal as a high-level verification language. Using class libraries with SystemVerilog can take this a step further by enhancing productivity and enabling better, more efficient reuse between engineers and between projects. The Verification Methodology Manual (VMM) class library was one of the first SystemVerilog class libraries available, and has been widely adopted. The Universal Reuse Methodology (URM) class library has more recently become available, and while it is similar to VMM in many respects, there are also some important differences. This paper, voted the Most Valuable Paper at CDNLive! Silicon Valley 2007, describes the process of converting an existing testbench based on VMM class libraries to one based on URM class libraries. It highlights which aspects of the conversion were straightforward and which aspects required more attention. The session concludes by summarizing the similarities and differences between the two approaches, and any potential advantages achieved by doing the conversion
Kelly D. Larson,
Analog Devices
| | Technical Paper | | 09/27/07 | |
| | Interview: New SoC Functional Verification Kit Kicks it up a Notch
Amjad Qureshi, SoC Functional Verification Kit architect for Cadence, talked to cdnusers about the new Kit that was introduced in August. The Kit provides example verification plans; transaction-level and cycle-accurate models; design and verification IP design from Cadence and third parties; scripts; and libraries. Why the need for a new Kit, and what does it mean to the design community? That’s what we asked Amjad.
Amjad Qureshi,
Cadence Design Systems
| | Interview | | 08/29/07 | |
| | Metric-Driven Methodology Speeds the Verification of a Complex Network Processor
In my business unit, we often struggle to keep our hardware in sync with the software
schedule. Doing so requires a great deal of resources. So it was no small feat when the
verification flow for one of our recent designs, the Programmable IP Services Accelerator
(PISA) FPGA in development, was completed ahead of schedule and well before the
system software was delivered. In fact, it’s unprecedented and has really turned some
heads within our various groups.
Was this a reflection of mistakes made by our team working on the software side?
Absolutely not. This story really has much more to do with what our small hardware
verification team did right. What we experienced was an interesting example of how
introducing new verification methodologies into a real-world design environment can
improve overall productivity and process management.
On the project, we employed a metricdriven process-based approach for the functional
verification of our FPGA. I’m eager to tell you how it worked because if you want to
save some time, reduce risk, and further improve your verification process, you may want
to apply some of the lessons we learned.
Jean-Paul Lambrechts,
Cisco Systems
| | Technical Paper | | 08/22/07 | |
| | Defining New Metrics in Enterprise Manager (Input Metrics)
Metric driven verification is all about planning the objective metrics that you’ll use to gauge the completeness of your project and then using those metrics to increase your project’s productivity, predictability and quality. But first, you have to capture the metrics
Hamilton Carter,
Cadence Design Systems
| | Technical Paper | | 08/22/07 | |
| | Customizing and Extending Enterprise Manager Functionality (A Primer)
Enterprise Manager provides several tools for tracking and analyzing over 100 design and verification project metrics. Using those metrics, Enterprise Manager automates many design and verification tasks such as progress tracking, regression execution, low power verification, and debug triage to name a few.
But, what if you want to track a metric that’s not built into Enterprise Manager? What if you want to connect several automated tasks into a comprehensive automated flow? Enterprise Manager provides an extensibility interface that allows users to add new functionality or automate existing functionality. The extensibility interface exposes parts of Enterprise Manager’s functionality as an object model so that users can customize the exposed functionality.
Hamilton Carter,
Cadence Design Systems
Paul Carzola,
Cadence Design Systems
| | Technical Paper | | 08/01/07 | |
| | Testbuilder class library, examples and documentation
TestBuilder refers to versions 1.1 through 1.3 of the TestBuilder C++ class library. The similar CVE class library consists of Cadence extensions to the OSCI SystemC Verification (SCV) standard. Both TestBuilder and CVE provide features to aid complex test development such as: data structures, dynamic memory and tasks, reentrancy and recursion, support for object-oriented programming, complex constrained randomization, and temporal checking facilities.
Testbuilder and CVE are similar, except that:CVE uses naming conventions that are consistent with SystemC, CVE uses SystemC as the threading kernel and CVE needs to communicate to host simulators using the host simulator's native SystemC communication mechanism to improve performance and reliability. In most cases, there is one-to-one correspondence between the Testbuilder and CVE APIs.
This how-to kit contains Testbuilder C++ class library, examples and documentation
| | How to Kit | | 08/01/07 | |
| | Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilog
Verification reuse is one area we are focused on because it enhances reliability and saves a tremendous amount of time, especially when developing a complex protocol such as a Gigabit Ethernet. In our case we used the Cadence Incisive Plan-to-Closure Methodology that features the Universal Reuse component of Plan-to-Closure with SystemVerilog. This paper takes a close look at the protocol we were developing and many features of this methodology we incorporated into our flow that helped us successfully complete the task.
Sarvana Kumar,
TATA ELXSI Limited
Jagvinder Yadav,
TATA ELXSI Limited
Gaurav Singh,
TATA ELXSI Limited
| | Technical Paper | | 07/30/07 | |
| | Methods to Improve Verification Quality on the Module Level
This presentation, winner of the Best Paper Award in Functional Verification at CDNLive! EMEA, discusses the challenge of obtaining high quality verification on SoC projects with many new or revised modules. To achieve this, Siemens AG Automation and Drives uses a consequent Plan-to-Closure Methodology. This allows smart combinations of several verification methodologies, while high-quality coverage-driven verification remains the most important task.
Markus Gross,
Siemens AG
| | Technical Paper | | 06/15/07 | |
| | UltraSPARC Processor Emulation Verification: Getting HW/SW right the first time
This paper, presented at DesignCon 2007, depicts revolutionary usage of emulation technology at Sun in general and in particular the role it played in verification of our latest generation CoolThreads
UltraSPARC T1 processor. Emulation stepped in to take on challenges of running long
directed, random self-checking and DFT diagnostics just where traditional SW simulators
run out of gas. Our system models are so large that SW simulators literally come to a
crawl. We will discuss emulation modeling, capacity and performance optimization
techniques along with key factors enabling our success. We will also describe
methodologies to enable firmware and SW development and testing prior to design tape
out. We were able to cut the product development cycle in roughly half. The focus of this
presentation is to depict issues related to verification of large SoC and innovative
techniques employed to resolve them successfully.
Jai Kumar,
Sun Microsystems
| | Technical Paper | | 06/07/07 | |
| | QLogic Depends on Verification for First-time Silicon Success
Tom Paulson, principal engineer for QLogic’s system simulation in the Switch Products Group, talked to cdnusers about his challenges, methodology, and verification process for their complex chips.
Tom Paulson,
QLogic
| | Interview | | 05/10/07 | |
| | IEEE 1647-2008 standard update brings greater interoperability
An interview discussing the current status of the IEEE 1647-2008 standard update and the benefits to Verification designers.
Andrew Piziali,
IEEE
| | Interview | | 04/30/07 | |
| | The Challenge is No Longer the Design, it is the Verification
I was brainstorming yesterday with some Verification forum moderators and I raised the idea that our challenge is no longer about the design, it's about the verification. I think the overall idea I was attempting to get to was something I think is happening to design projects, and I know it is happening to ours
Tom Paulson,
QLogic
| | Commentary | | 02/21/07 | |
| | Incisive Generic Software Adapter (GSA) Product Review
The Generic Software Adapter (GSA).is part of the Incisive Software Extensions (ISX). ISX is part of the ESL Verification solution that was announced by Cadence in Dec 2006.
GSA extends Specman Elite to drive and monitor software in the same way that is done for hardware. With GSA software calls or internal signals can be bound to e ports like HDL signals. This allows the user to cross hardware and software coverage items and a reactive stimuli generation dependant on hardware or software states.
Ernst Zwingenberger,
El Camino GmbH
| | Product Review | | 02/12/07 | |
| | Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach
This paper, presented at DVCon 2007, presents flows and methodologies for using plan-driven verification
testbenches with accelerated verification engines via transaction oriented interfaces. It describes how to reuse stimulus generation, coverage analysis, checking and error handling in reactive and regression environments while optimizing the testbench architecture and modeling style for high performance verification.
Leonard Drucker,
Cadence Design Systems
Shabtay Matalon,
Cadence Design Systems
Kanwarpreet Grewal,
Cadence Design Systems
Michael Stellfox,
Cadence Design Systems
| | article | | 01/12/07 | |
| | Implications of a Configuration Based Verification Environment
A Configuration-Based Verification Environment is built using named configurations, each of which describes a set of modules, their interconnections and parameterization of tools applied in their simulation or analysis. Multiple configurations exist in the same workspace to support the sharing of components. The Configuration-Based Verification Environment supports concurrent operations over multiple configurations, allowing one to regress multiple variants of a configurable design in a unified framework. A 'flow' is the generalization of a specific verification task as performed over a generic configuration. In our Configuration-Based Verification Environment, a typical simulation flow includes a generated top-level test harness, configurable RTL, extracted netlists, programmable functional models, and behavioral models of custom logic. We allow configuring architectural parameters of the design, the collection of models used, the simulator to run, the names of PLI libraries to include, memory limits of the target execution host, and the machine architecture on which to run jobs. Embracing this level of configurability and managing it successfully requires identifying and adhering to a few basic principles. This paper, winner of the People's Choice award at CDNLive! Silicon Valley reviews the components of a Configuration-Based Verification Environment. Principals guiding the construction of such an environment will help others avoid pitfalls that impede configurability. Lastly, we give some suggestions to tool vendors on how their tools can better support large scale configurability
Tom Sheffler,
Rambus
| | article | | 10/18/06 | |
| | Xtreme Series Product Review
Xtreme Server is a simulation acceleration and emulation system. Sun Microsystems uses simulation acceleration in the early phase of the project, and transitions to targetless emulation as the design matures. Targetless emulation lets them obtain the higher speed-up necessary for long simulations
Jai Kumar,
Sun Microsystems
| | Product Review | | 09/24/06 | |
| | Coverage Driven Methodology for Verification of SoC Hardware and Software Corner Cases
As design complexity and embedded software content continues to increase, it is becoming more and more important to verify specific corner cases that occur between the interaction of hardware and software in SoC Designs. The primary challenge is to get the hardware and software into specific states so important conditions can be observed and measured using functional coverage. When software development takes place on hardware prototypes or final system hardware creating these complex corner cases and measuring them is nearly impossible due to lack of visibility of the states of the hardware design. A simple, but challenging example is the removal of a smart card when the embedded software is in all possible states to make sure the system will not crash or hang when the smart card is removed. There are many other corner cases that are never verified because they occur infrequently in the final system and are difficult to create during system testing. This session describes a methodology using the techniques of coverage driven verification (CDV) including constrained-random generation and functional coverage that have traditionally been applied to hardware verification and applies them to the embedded software and the mixed hardware/software design. The application of CDV to embedded software results in higher quality verification of corner cases and increased software quality with the application of functional coverage metrics. The methodology is built on the Incisive Enterprise Specman Simulator. Examples are also provided on how to use the methodology with the Incisive Design Team Xtreme Server
Jason Andrews,
Cadence Design Systems
| | Commentary | | 09/21/06 | |
| | Constrained Random Data Generation Using SystemVerilog
SystemVerilog offers a number of new constructs to help with generating stimulus more efficiently. One of the most powerful is the class construct. By using classes, items can be specified to be randomly generated along with constraints to make sure the data is meaningful. Classes can also contain methods which are functions to further manipulate or present the data. This presentation will cover all those aspect of classes to show how to create, use, and extend classes for constrained random generation.
Tim Pylant,
Cadence Design Systems
| | Article | | 09/20/06 | |
| | UltraSPARC Processor Verification: Pet Peeves and What's so Cool about Xtreme HW!
With reduced time-to-market and shortened product design cycles, it is now important, more than ever to get the product right the first time! And this is no different for latest generation CoolThreads UltraSPARC T1 processor. The UltraSPARC T1 processor represents one of the highest throughput and most eco-responsible processor featuring unique multi-core, multi-threaded design posing new verification challenges. We embraced this verification challenge by enhancing verification efficiency by adapting aggressive changes in methodology, state-of-art tools and technologies. We at Sun strongly support usage of acceleration/emulation technologies to perform integration/verification tasks prior to tape-out that are traditionally performed after arrival of silicon. Acceleration from multiple vendors is a key ingredient of our block, chip and system level verification methodologies. This paper will discuss usage of Xtreme technology at Sun in general and in particular the role it played in verification of our latest generation CoolThreads UltraSPARC T1 processor. We were able to cut the product development cycle in roughly half. In this paper I will share my pet peeves and the cool features of the Xtreme technology. Pet peeves - what were the challenges in using Xtreme HW and how we over came those challenges to make it work successfully. The focus of this presentation is not on just articulating issues, but rather the innovative techniques employed to overcome the issues. So cool - what worked well for us. The idea here is that the readers will walk away with useful tips to enhance their verification productivity.
Jai Kumar,
Sun Microsystems
| | Technical Paper | | 09/19/06 | |
| | Assertion-Based Coverage-Driven Verification
Using a simple testbench that reads and applies stimulus and write outputs for post-processing validation is not keeping up with the verification demands of today's chips and IP. But, migrating to object-oriented testbenches and other advanced verification techniques can be intimidating for many engineers and possibly overkill for many of today's verification needs. Therefore, alternative verification methodologies somewhere between these two extremes need to be explored. This session will discuss how assertion-based verification (ABV), along with coverage-driven verification (CDV), can be leveraged as a small step to a more efficient verification process that keeps pace with many of today's verification challenges at the module, block, cluster and even chip-level. The focus of the session will be developing meaningful assertions and coverage metrics that facilitate an efficient simulation environment. In addition, the concept of maximizing return-on-investment for assertions will be discussed in the context of a complete ABV flow including formal analysis, simulation, and acceleration/emulation. A recent customer experience of incorporating ABV and CDV methodologies will be presented during this session. Insights into the ease of adoption and value added to the overall verification flow will be discussed. Through the use of an ABV methodology that includes CDV, design and verification engineers can benefit from an environment that provides measurable insight into the correctness of their design, the efficiency of their simulations and whether the verification goals have been achieved.
Chris Komar,
Cadence Design Systems
| | Article | | 09/19/06 | |
| | Beyond the Compliance Checklist
While the trend to use more and more design IP has considerably reduced design effort per gate, it has had the exact inverse effect on functional verification effort. The majority of design and verification teams today use verification IP (VIP) in one form or another. In fact, VIP is essential for any complex protocol or bus standard (e.g., PCI Express or AMBA AHB/AXI). Teams achieving the greatest success combined VIP use with a verification reuse strategy and a methodology that begins with an initial plan and goes all the way through to full verification closure. VIP’s end goal is to improve the verification process while reducing your verification project’s risk profile. However, the decision as to which VIP to use has only gotten more complicated. his article will help you optimize VIP selection decisions. It will familiarize you with the various classes of VIP and the key issues to consider in your VIP selection.
Pete Heller,
Cadence Design Systems
Erez Kovshi,
Cadence Design Systems
| | article | | 08/18/06 | |
| | Adelante VD32040 Core and Subsystem Verification: What is Verified Where?
This presentation, rated one of the best presentations at CDNlive! EMEA 2006, gives an overview of the verification methodologies used to verify a DSP, both core and sub-system. The Device Under Verification is an embedded vector processor (Adelante™ VD32040). The VD32040 is developed within DSP Innovation Center, which is part of Philips Semiconductors.
For the verification of the complete VD32040 various methodologies and verification environments are used. The challenge is the trade-off between minimizing the number of used methodologies and having a good verified product. The core itself is verified using the VD32040 simulator as a reference model. In this environment SpecMan is used for generation of a random DSP program, comparison of the internal registers (RTL vs. simulator) and implementation of functional coverage items. Most of the components in the VD32040 subsystem are verified using scoreboards written in ‘e’. This is done in an environment in which the VD32040 core is replaced by eVCs. Virtual sequences are used to generate corner-cases, e.g. transactions simultaneously valid on various interfaces.
Roger Witlox,
Philips Semiconductor
| | Article | | 07/15/06 | |
| | Merging to Unified Pre-sil Post-sil Validation Environment
This presentation describes how Intel successfully uses Specman for verification of a design post-silicon. It presents the benefits of using coverage driven verification to enhance the quality and debuggability of projects. The approach is detailed, including key factors that others must assess to determine when this should be applied to their projects."
Assaf Eldan,
Intel Corporation
| | Technical Paper | | 07/11/06 | |
| | An Introduction to Aspect Oriented Programming in "e"
This paper is taken from a forthcoming book about Aspect Oriented Programming. Not just the acadmeic stuff that you'll read about elsewhere, although that's useful, but the more pragmatic side of it as well. Its about using AOP in ways that will make your code easier to write, easier to use, easier to reuse, and in a way that will help you meet your project schedule. It gives real examples of AOP in action, and throws in some guidelines on how to organise your code so that you can actually find things again. Along the way it describes what an aspect really is. It might even give you some ideas on how to avoid problems in OOP.
David Robinson,
Verilab
| | Article | | 07/10/06 | |
| | Verification Tracking and Total Coverage
While it is normally no problem to state that a design is implemented completely it is hard to say that you're ready with the verification.
Against this background Siemens A and D together with Cadence have developed a process to track all the measurable results in verification. In this paper, presented at DATE 2006, the author shows how apart from the functional coverage related to SpecMan-e, other coverage items like PSL statement coverage or simply a list of testcases can be successfully applied to the design. In addition to this functional coverage the so called structural or code coverage is also available telling us when we are not ready. Putting these altogether gives us what we call the "total coverage" which is to be tracked with the tool vManager from Cadence. While working on an OAP project we have defined the process and implemented the necessary modifications and extensions to the vManager. For the time being several verification plans are integrated in this verification tracking environment.
Andreas Dieckmann,
Siemens AG
| | Article | | 07/03/06 | |
| | DSP Sub-System: Spec to Closure
The SPEC to closure presents the verification process and flow of a sub-system from the ARCH spec stage, through methodology aspects, standalone environments and system-level verification. The presentation highlights the challenges in verification and presents a verification strategy to get to a test coverage of 100%.
Ran Snir,
CEVA
| | Technical Paper | | 06/19/06 | |
| | An Analog Mixed-signal Verification Kit for Verification of Analog-Digital Circuits
The greatest obstacle to a System-on-Chip [SoC] design team’s success is verification. Combining the complexity of digital verification with the increasing integration of larger and more sophisticated analog circuits, the problem is getting exponentially worse. This trend not only presents a challenge to the verification engineers, but to the industry as a whole. If verification of digital sub-systems is based on advanced techniques such as constraints capture, randomized or pseudo-randomized stimulus-generation and result collection with functional coverage evaluation, on the other side the use of hand-coded analog blocks models, manually-verified within a digital verification environment has been sufficient to provide confidence in a mixed-signal design to sign-off prior to submitting it for fabrication. However, due to greater levels of integration, changes in process technology and increasing market pressures and risks, an automated and metric-driven methodology is now required. YOGITECH’s proposed approach combines digital and analog circuit verification, providing engineers with a methodology and a set of intellectual properties to interface verification tools with mixed signal simulators. This approach allows extending to analog and mixed signal domain concepts and techniques widely used in state-of-art object-oriented digital functional verification. Using a Bandgap cell as case study, the paper shows how the presented solution allows a significant improvement in verification productivity and quality.
Monia Chiavacci,
Yogitech SpA
Dr. Riccardo Mariani,
Yogitech SpA
Egidio Pescari,
Yogitech SpA
Dr. Giuseppe Bonfini,
Yogitech SpA
| | Article | | 06/16/06 | |
| | SystemC TLM for Complex IP’s Verification
This project illustrates the SystemC TLM-based verification flow in place today for IP in the context of a virtual SoC reuse methodology, allowing a smooth migration between levels of abstraction: Virtual SC TLM soc simulation, RTL co-simulation, RTL co-emulation, SoC simulation and SoC emulation.
For IP verification the strategy is to apply a test scenario with a transaction level testbench on a golden reference model to predict test signature, then replace it by the RTL while reusing transactional testbench and all tests. The same golden reference model is also used in a SystemC TLM virtual SoC for low level driver SW development before silicon and a subset of IP verification test scenarios are also reused by SoC verification to ensure design integration correctness.
Laurent Ducousso,
STMicroelectronics
| | Technical Paper | | 06/16/06 | |
| | Extending a Coverage Driven Verification Environment with Real Software
HW/SW co-simulation is often carried out on complex chip level verification environments, executing software on the simulated target CPU or connecting an instruction set simulator to the hardware simulator. In this presentation, we discuss the value of extending a coverage -driven subsystem or module level verification environment using real software. The software will be executed on the host computer and embedded into a layered hardware verification environment. The software raises the level of abstraction and saves work in implementing the stimuli generation part of the test bench. On the other hand the power of coverage- driven verification methodology will be applied to the software as well. This environment, consisting of a simulated hardware subsystem and the software, executed on the host computer, is simplest to debug
Ernst Zwingenberger,
El Camino GmbH
| | Technical Paper | | 06/16/06 | |
| | Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project
Project management and automation is quickly becoming the most critical element in the overall design and verification process. The key ingredients are good overall specification development that leverages planning with metric based checkpoints. The mentality of “beginning with the end in mind” allows for optimal resource usage, much higher design quality and realistic schedule estimates. Despite all the best planning, changes in requirements happen up to the last possible day. By following the simple guidelines in this paper, "good" planning based on verification managment can be realized. Your organization will benefit as all stakeholders begin to leverage the ability to capture and review the verification plan as you drive you next design to closure.
Ilana Golan,
Cadence Design Systems
| | Article | | 06/10/06 | |
| | Simplifying SoC Verification using a Generic Approach
This presentation describes an e Verification Component (eVC) that has been used in the verification of several independent bus based SoCs with only minimal modification. The user simply describes the topology of the design and environment to the eVC, and the eVC uses this information to instantiate the correct bus eVCs, to create the required scoreboards, to generate customized functional coverage, to control the default stimuli so that only realistic transactions are generated, and to perform full bus infrastructure verification.
Individual testbenches can define their own view of the design to reduce the scope of the testbench, improve performance, and reduce third party license usage. The eVC greatly increases the user’s productivity by automating many of the trivial but time-consuming aspects of an SoC testbench. It has proven to be so generic that certain tests can be moved between SoCs without modification, and RTL bugs have been detected within one day of receiving the initial RTL and starting the verification effort. The “self healing” nature of the testbench makes mid-project design changes trivial to deal with.
Once a design’s bus infrastructure has been verified, the eVC provides an advanced platform on which to build the rest of the verification environment."
David Robinson,
Verilab
| | Article | | 06/10/06 | |
| | Verification Languages: 3 points to ponder beyond "which one?"
No matter the verification language chosen, whether one or multiple, verification planning, process management and qualified metrics, are critical to achieving predictability, reducing risk and ultimately delivering your product. This paper suggests questions to pose when choosing your verification language.
Ann Germany,
Globetech Solutions
Shankar Hemmady,
Cadence Design Systems
| | Article | | 06/06/06 | |
| | Incisive Interoperability Design
This document describes the details of the Incisive Interoperability Design (IID). The intent behind IID was to create a functional working design that could be used as a vehicle for applied use of all Enterprise Family, and or Design Team Family tools and HDL languages operating together. The expectation was that such a design would return a number of benefits.
IID can be used to verify that all the tools that support the EF/DTF verification method and solution work together in a design that is big enough to support use of all EF/DTF tools and HDL languages, yet small enough for debugging and isolation of bugs identified in software under test. IID serves as a tool to demonstrate how to setup a design to use EF/DTF tools and supported HDL. IID can easily be modified to execute application specific or focused testing. Being a comprehensive design, meaning that the design covers several tools and languages, the design can be used to quickly validate all of the included tools and languages.
This how to kit demonstrates how to use DF/DTF tools using a small design as an example. The pdf document listed below explains the procedure of setting up the environment and running the tool; the files in the zip file are an actual example of a small cpu design.
Eric Williamson,
Cadence Design Systems
| | How to Kit | | 05/08/06 | |
| | Leveraging Assertions in System Verilog Testbench to get to Closure
This paper discusses some best practices in functional verification by making use of
SystemVerilog for testbench, assertions for static or dynamic checking and functional
coverage. It also discusses how to construct different components of verification
environment (for example BFMs, monitors, stimulus generation etc.) for ease of reuse in
multiple projects and platforms. It illustrates through a complete verification example -
how designers can compose their block level environment with assertions, coverage and a
testbench that finds more bugs and is also reusable.
Tim Pylant,
Cadence Design Systems
| | Article | | 03/23/06 | |
| | Transaction-based Simulation Using SystemC/SCV
Fujitsu Kyushu Network Technologies has accomplished two successful projects using the SystemC verification library with Cadence Design System Incisive unified simulator (IUS). The first project involved the design under verification written in Verilog and other parts of the tesbench in SystemC/SCV. Transaction-level models (TLMs) of th eCPU and RAM were written in SystemC. The second case study describes a test environment consisting of two frame generator TLMs that send random traffic to a VHDL design under verification.
Eisuke Yuri,
Fujitsu Kyushu Network Technologies, LTD
Neyaz Khan,
Cadence Design Systems
Chris Dietrich,
Cadence Design Systems
| | Article | | 03/15/06 | |
| | eRM Based, Full ML Reuse Methodology
Project management and automation is quickly becoming the most critical element in the overall design and verification process. The key ingredients are good overall specification development that leverages planning with metric based checkpoints. The mentality of “beginning with the end in mind” allows for optimal resource usage, much higher design quality and realistic schedule estimates. Despite all the best planning, changes in requirements happen up to the last possible day. By following the simple guidelines in this paper, presented at CDNLive! Israel, "good" planning based on verification managment can be realized. Your organization will benefit as all stakeholders begin to leverage the ability to capture and review the verification plan as you drive your next design to closure.
Shlomi Sperber,
Texas Instruments
| | Article | | 03/10/06 | |
| | System Verilog Workshop Tutorial from DVCon 2006
This Powerpoint presentation from DVCon 2006 was given as a workshop tutorial. The presentation shows how to increase designer productivity, enhance testbench capability using SystemVerilog.
Tim Pylant,
Cadence Design Systems
| | Article | | 02/26/06 | |
| | Verifying the TriCore2 Multithreaded Microprocessor
This paper from DesignCon 2006 describes the verification of TriCore2, Infineon’s second generation 32 bit multithreaded microprocessor. TriCore2 is aimed at the embedded market, including
safety critical applications, and hence considerable effort was put into its verification.
State-of-the-art verification methodologies were used, including directed and coveragedriven
random testing, assertions and formal methods. The use of these is detailed along
with the sign-off criteria used, and results reported. Since a real project is described, a
non-idealised view is presented and the lessons learnt are given. The particular challenges
presented by verifying a design with the large functional space of a complex processor
are highlighted.
Fabio Bruno,
Infineon Technologies
Tim Blackmore,
Infineon Technologies
| | Article | | 02/26/06 | |
| | A Systematic Transaction-level Modeling and Verification
Design flow by transaction-level (TL) prototyping has received a great deal of attention as a solution of system-on-chip challenges that cannot be addressed by traditional design methodologies. This paper, delivered at the DVCon 2006 conference, addresses the issue of systematic TL modeling and verification methods. Specifically, (1) a systematic design modeling flow with a set of well-defined transaction protocols and TL model verification methods are proposed; (2) We show comprehensive details on architecture (bus, memory, basic blocks) exploration results obtained by using our TL modeling and verification methodology for movie capture application, which interwinds Camera I/F, two DMAs, LCD buffer, SDRAM, and MPEEG HW accelerator.
Dr. Junhyung Um,
Samsung Electronics
Woo-cheol Kwon,
Samsung Electronics
Dr. HoonSang Jin,
Samsung Electronics
Dr. Kyu-Myung Choi,
Samsung Electronics
Dr. Jeong-Taek Kong,
Samsung Electronics
Soo Kwan Eo,
Samsung Electronics
Dr. Taewhan Kim,
Seoul National University
| | Article | | 02/22/06 | |
| | System Validation: An in-depth Comparison of FPGA Prototyping to Emulation at Sciworx
With the worldwide trend toward digitalization, design and software complexities are steadily growing while design and product lifecycles are shrinking. Hardware, software, and overall system components all must be ready at the same time. And system functionality must be verified in conjunction—prior to fabricating silicon. As a result, design and software teams must improve productivity and quality.
Verification is a major roadblock in creating the final product and is a key component of timely market release and success. Prior to real silicon there are only three verification options: FPGA prototyping, simulation, and emulation. This article summarizes the Sciworx verification team’s experiences with a 1.2 million-gate multimedia design IP core including an ARM9™ family processor. The Incisive® Enterprise Palladium® system from Cadence® Design Systems was evaluated against FPGA prototyping.
Volker Wegner,
Cadence Design Systems
| | Article | | 02/21/06 | |
| | Verification Planning to Functional Closure of Processor-based SoCs
In today's fast-paced electronics market, time to first pass, fully functional silicon is the ultimate determinant of financial success. Functional verification typically ends up being the most unbounded problem in the flow. While teams struggle with verification, the root cause of this struggle is the lack of a comprehensive verification plan and automation of the verification proess that leverages the plan. This paper describes the problem and presents an approach to verification planning that leads to a high quality plan. It concludes with an example of verification automation, specifically highlighting the connection to an executable verification plan.
Andrew Piziali,
Cadence Design Systems
| | Article | | 02/07/06 | |
| | Why is My Customer a Better Verification Engineer than Me?
Why is it that after months of directed and random testing you were not able to find a bug
that your customer found within two days of receiving samples? Is there anything wrong
with your directed and random testing? Should you blame it on faulty assertions? Could
it be that you did not run your simulation long enough? The intention of this paper, presented at DesignCon 2006, is to answer those questions by analyzing past mistakes and proposing a new approach in
writing and executing a verification plan.
Alfonso Iniguez,
Freescale Semiconductor
| | Article | | 02/06/06 | |
| | Incisive Plan-to-Closure Methodology Overview
Verification of contemporary hardware, chips and system designs introduce a myriad of challenges for design and verification teams:
The challenge is to optimize the entire verification process to deliver the highest quality, with productivity and predictability.
This technical webinar will provi |
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