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| Session 1.1: Full Chip Verification of Multi-Core SoC for Mobile Application Engine
The convergence of various applications into the mobile space is driving the mobile application engine to be more complex. Consequently, the demands by the high-end application are mostly met by Multi-processor SoC architecture. Verification of complex Multi-processor SoC (MpSoC) throws up different uplift for the challenges in the chip level verification arena. It is obvious that verification complexity increasing linearly or even exponentially depending on the number of Cores, IPs and interconnects infrastructure in the MpSoC. This presentation shares our full chip level verification/validation methodology and verification environment which was adopted for an application engine of mobile multimedia chip. The MpSoC verification methodology includes the efficient run-time reduction by SystemC transactor substitution, automated initialization and Simple debug method on native simulation setup. This presentation will also share the interoperability setup which used as part of chip level verification.
BadriSeshadri,
NXP
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| Session 1.2: Quality & Confidence Improvement On OCP IP's Using Cadence OCP ABVIP
We usually source a lot of 3rd party IP's for our sub chips and Socs and most of these IPs transact via Open core protocol (OCP) interface as an on-chip-bus interface. We were looking for a methodology or tool which could quickly check the OCP protocol compliance for all OCP IP's before integrating them with other IPs. Existing methodologies were broadly simulation based and needed some effort in setting up the environment for every OCP IP to check the protocol compliances, the primary concerns being time and re-use. Cadence Incisive Formal verifier (IFV) with OCP ABVIP enabled us to do OCP protocol compliance checks on our IPs quickly and completely. Incisive Formal verifier uses sophisticated algorithms to conclusively prove or disprove that a design behaves as desired for all possible operating states. This methodology has the capabilities to track corner case bugs in a design in a short span of time. Cadence OCP ABVIP is an assertion based verification IP, which is plug and play compatible with the designs. It comes along with a complete set of OCP Master and Slave properties. Based on DUT configuration, the Master/Slave Properties may be used as either constraints or assertions.These approaches have resulted in a significant 30%-40% cycle time reduction when used across several IPs in our OMAP3x program and they found some critical Issues in the design. We would be extending this practice across all IPs in the upcoming OMAP4x program.
This paper talks about our OCP IPs, existing simulation based verfication methodology, Formal based methodology using IFV and OCP ABVIP, case studies and future scope.
AneetAgarwal,
Texas Instruments
MithunGhosh,
Texas Instruments
TejinderSyan,
Texas Instruments
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| Session 1.3: Integrating Design IP and Verification IP to Ensure Quality and Predictability
Customizing IP is critical for customers to provide optimized implementations that differentiate their products in the market place. However, when a design team needs to modify the design to integrate an IP block, effort and risks increase dramatically. Rambus and Cadence highlight the benefits of working together to provide complete IP solutions that combine highly configurable design IP with state-of-the art verification IP to ensure quality and predictability for Soc designers. This paper will describe the methodology used to speed up the configuration and verification process and provide a differentiated deliverable for the customer. Rambus PCI Express controller design will be used to highlight the importance of sophisticated verification methodology to ensure the verification process is complete and easy for the end user. The benefits of the plan to closure methodology will be highlighted including the use of customized verification plans. The combination of independently developed design IP and verification IP provides the user confidence in the quality and integrity of the customized design. The result is a highly predictable design IP for the customer along with an integrated verification environment that is reusable, configurable and provides more visibility into the design IP to get to the end goal much faster
SriramSwaminathan,
Rambus Chip Technologies
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| Session 1.4: SCE-MI Based VIP : A Catalyst To Accelerated Emulation Based Validation & Debug
Increasing chip complexity has always presented new challenges to verification and validation engineers. It's important not only to validate all functional scenarios but also to have fast debug. Pure functional models provide fast and easy to use high abstracted system, but lacks speed if cycle accuracy is implemented. Hardware Acceleration Solutions offer good speed but debug and ease of usability is a concern. SCE-MI based VIP is a solution which tries to take advantage of fast emulation world and ease of higher abstracted stimulus generation. VIP is essentially a hybrid verilog plus SystemC model with implementation of SCE-MI APIs which establishes communication between DUT on emulator to SystemC testbench. SCE-MI allows a high level transaction based model to talk to design on Hardware Platform and presents a platform where engineer can write high level tests to validate system. Here HDL mapped on the emulator gives speed and cycle accuracy, at the same time user is also gifted with traditional SW based debugging goodies like waveforms, traces, prints etc. In this case study we will show how we used CADENCE's PCIe TBA VIP to develop a product which is used to test PCIe interface in various configurations. An enhanced PCIe controller (licensed IP) was recently added to design as an interface to external PCIe target. Two such controllers were introduced in the design. Testing this design on hardware platform was a challenge as it was required to add another PCIe target to test it. To test stimulus generation from both side, emulation team tried connecting two DUTs back to back but this was again a daunting task due to various clock and sync issues. TBA VIP came as a relieving handy solution for this. TBA VIP was connected to this interface on DUT and we could test system in multiple configurations. It could be used as both a root-complex as well as an end point. TBA VIP can play the dual role of real target to interface as well as of initiator so stimulus could be generated from both directions. TBA VIP gave access to transaction packets whose fields could be manipulated to test error injections.
ManishBaphna,
Freescale Semiconductor
SharadSharad,
Freescale Semiconductor
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| Session 1.5: How Do I Leverage My Investment In Traditional Testbenches While Adopting Modern Verification Techniques? - A Case Study
Functional Verification of ASICs and SoCs is seen as the single biggest challenge in churning out more and more System-on-Silicon atleast from the concept to netlist phase. This has been proven by recent tapeout statistics that reveal that in a typical design cycle ~70% time is spent on verification. The challenge is no more in “how much can you integrate into one-chip”, rather it is “how many IPs can you meaningfully integrate to do something useful”. This fundamentally requires advanced verification techniques such as Constrained Random Verification (CRV), Coverage Driven Verification (CDV) and Assertion Based Verification (ABV) - including formal analysis (Model Checking). Several techniques and languages have been evolved over the last decade that address this problem such as the emergence of IEEE-1647 (e language), IEEE-1800 (SystemVerilog) etc. But the reality is even today there are a large number of designs being verified with traditional, conventional testbenches and that means presence of a huge set of legacy, time tested verification components such as drivers, monitors, checkers etc. While almost every DV team agrees the necessary to move on to the newer, advanced technologies for verification, the investment done in legacy components is too much to throw away overnight. So a pragmatic verification methodology should account enough for the smooth integration, co-existence of these legacy components and should build on top of them to bring in the benefits of CRV, CDV and ABV. In this paper we show how the legacy, HDL based verification components (VCs) can be reused with little or no change in a full fledged SystemVerilog environment thereby getting the best out of both worlds.
AjeethaKumari,
Contemporary Verification Consultants
BagathSingh,
Contemporary Verification Consultants
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| Session 1.6: eScape to System Verilog: The Surprises
Radio Frequency Identification (RFID) Class-1 Generation-2 protocol is a complex wireless serial interface protocol with several levels of abstraction. That is, the Commands and Responses which make up the communication consist of sequence of bits and the bits are encoded into symbols before being sent out. These are then reconstructed in the target. A High-level Verification Language (HVL) like e is a must for verification of a design implementing this protocol. Verification using e, however, requires two simulators: one for the verification code (in e) and one for the design code (such as in Verilog). System Verilog on the other hand is a single language with both Design as well as HVL capabilities and would hence require a single simulator for verification. The porting of a e Testbench into System Verilog hence assumes importance. This activity had, however, several surprises and learnings. This paper discusses some of the more important ones.
Srinath BPai,
National Semiconductor
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| Session 1.7: Reducing Complexity in Formal Analysis
Formal Analysis results are highly dependent on how the assertions and constraints have been used for verification. Many-a-times it so happens that some constraints and/or assertions end up creating a conflict among themselves thereby adding complexity to the process. As a result, the verification runs take huge run times and end up with Explored Depth (ED) rather than giving Pass or Fail results. Explored Depth is reached when the tool needs more than defined efforts, to prove an assertion. It takes a lot of effort on the part of verification engineer to convert these EDs into Pass or Fail results within the project timelines. The hidden key issues leading to Formal Complexity are: 1.) Large Cone-Of-Influence of a property to be proven, 2.) Usage of constraints and/or assertions creating conditions which are not feasible in real time or are opposing in nature and 3.) Trying to prove properties that verify the data path rather than the control path. This paper deals with these complexities and how these can be reduced by using various techniques. Focusing the properties only on an independent and relevant part of design, instead of the code that does not contribute functionally to the part of design being verified, can reduce the formal complexity to a great extent. Some of the techniques implementing this strategy are: Property partitioning, Property coding, Black-boxing, etc. These complexity reducing techniques have been successfully implemented for RTC (Real Time Clock) and Clock Generation IPs.
PrashantBhargava,
Freescale Semiconductor
NeerajMangla,
Freescale Semiconductor
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| Session 1.8: Coverage Driven Verification Of A Complex DSP System – Implementation & Learning
Today’s System-on-Chip (SoC) designs integrate highly complex IP (Intellectual Property) subsystems to achieve time to market. Verification methodologies that are extendable, reusable and provide coverage metrics for objective assessment of verification achievement are key criteria used for complex SoC verification. High-level verification languages and tools for random functional verification address part of this need. Tools like Specman provide functional coverage, but coverage assessment was done towards the end of verification cycle before Mask Order. This can result in redundant test database, lack of formally agreed coverage points, time and motivation to achieve 100% coverage. This paper describes the adoption of “functional coverage driven verification methodology” for the verification of a complex DSP System. In this methodology, Functional Coverage Plan (FCP) drives verification activities and development of test bench architecture to meet the coverage requirements. A good FCP mandates in-depth understanding of the design functionality by verification engineer/s with inputs from review by designer/s. During this project, we found that for SoC integration verification, FCP should include temporal cross coverage and coverage for conflicts across inter-connect buses of SoC sub systems. This paper describes the structure of resultant FCP. In this approach, environment would consist of robust design models, monitors and checkers to support completely random test cases, thus hitting functional coverage buckets and real life scenarios. vManager is used to collate the coverage and identify holes as per FCP goals. Functional coverage driven methodology provides better confidence of verification completeness through functional coverage metrics, reduced test database (50% less test cases), faster verification closure.
YogeshThombre,
LSI Research
AnuradhaTambad,
LSI Research
LokeshKumar,
LSI Research
Jayendra DwarakaBhamidipatti,
LSI Research
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| Session 1.9: Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog
In this era of reusable IP, multi-million gate ASICs and SoC designs, verification has become the major bottleneck because it consumes a significant portion of overall development efforts. Thus, it has become even more challenging for us to know when the verification of a design is complete and has met specified implementation criteria. These increasing design complexities have driven us to look at higher abstraction levels and modular approaches to help us develop an effective verification plan for our verification IP development. Verification reuse is one area we are focused on because it enhances reliability and saves a tremendous amount of time, especially when developing a complex protocol such as a Gigabit Ethernet. In our case we used the Cadence Incisive Plan-to-Closure Methodology that features the Universal Reuse component of Plan-to-Closure with SystemVerilog. This article recites the success-story of development of a Verification IP for Gigabit Ethernet Protocol using Cadence’s Cadence Incisive Plan-to-Closure Methodology and SystemVerilog Language (IEEE 1800-2005). It also explains various components of the VIP developed and interfaces between those components. The benefits of using uRM, the features that we incorporated into our flow that helped us successfully complete the task, some workaround techniques for tool limitations are also covered in this article.
JagvinderYadav,
Tata Elxsi
AnuradhaSingh,
Tata Elxsi
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