| | | | | | Custom IC Track: Accurate and Efficient Design of Pipeline A/D Converters
Real A/D converters have errors other than the limits of their resolution. These errors reduce the ENOB from the theoretical maximum. In some cases it is still necessary to examine detailed and complex
specifications to understand how A/D imperfections will impact your application. In most cases a single
metric which represents all of the degradations summed together is all you
need -ENOB. The trick is to convert all of the different contributors to a common fungible number and
sum them with the correct weighting factors. The best use of his technique is that the designer can
individually measure (with simple quick simulations) the imperfections of various sub-components of
the A/D and sum them to predict the A/D performance.
EricNaviasky,
Cadence Design Systems
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| | Custom IC Track: An RF Extraction flow using Cadence QRC-GXL and VAVO-VAEO
Intel Mobile Wireless Group is a world leader in WiFi and WiMax technologies. The RF team is working on integrated IC transceivers for these applications at advanced process technologies with industry
foundries. The RF team is located in Haifa, Petach Tikva and Oregon. Extraction for Intel's high-end
RF design has unique challenges, including high accuracy, modelling high frequency effects, advanced
process support, the need for a high-level of integration with the Cadence design flow and modelling
IR drop and electromigration accurately inside the flow. The paper will describe Intel's flow for RF
extraction, and how it addresses these requirements using Cadence's QRC-GXL technology, including
the extracted view flow, parasitic inductance and mutual inductance, Virtuoso Analog VoltageStorm
Option (VAVO) for IR drop analysis and Virtuoso Analog Electron Storm Option (VAEO) for
electromigration analysis.
DudiBen-Auen,
Intel MWG
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| | Custom IC Track: Custom IC Design Challenges and Solutions at 65nm and below
Advanced processes (65nm, 45nm, 32nm) pose special challenges to the custom IC designer. Process variability, optical effects, chemical-mechanical polishing (CMP) and other physical challenges need
to be taken into account earlier in the design cycle. The presentation will discuss these challenges, and
the technologies Cadence is bringing to market to address them.
RandyFish,
Cadence Design Systems
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| | Custom IC Track: Migration to Virtuoso IC61 Based on OpenAccess (OA)
Intel LAD is a world leader in the development of peripherals for LAN at advanced process technologies. Their analog team is adopting Cadence's Virtuoso IC61 platform, as part of their migration to a new process node. The presenters will discuss the productivity improvements they are seeing in the new
platform. The circuit design aspects, using Virtuoso Schematic Entry XL (VSE-XL) and Analog Design
Environment XL (ADE-XL), as well as physical design areas, using Virtuoso Layout Suite XL (VLSXL)
will be discussed. In addition, the presenters will discuss the experience they had in the migration
from CDB to OpenAccess OA.
ItaiZuker,
Intel LAD
YahavBar-Yosef,
Intel LAD
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| | Encounter Track: Manufacturing-aware Design Methodology to Address Systematic and Parametric Variation
As process nodes shrink to 65nm and 45nm, designers must consider a wider range of process effects on manufacturability. To achieve high-yield goals quickly, designers must make tradeoffs among timing, area, power, and yield. The SoC Encounter™ system offers accurate modeling of variations and critical area analysis based on the process technology node up front, helping you make the best design and implementation decisions.
Embedded in SoC Encounter GXL is a full array of CMP- and lithographically-aware yield enhancements, such as high-yield cell optimization, double cut via insertion, interconnect widening and spreading, and density uniformity optimization. These capabilities enable concurrent implementation and post-process optimizations that carry out your tradeoff decisions consistently, so you can minimize iterations and maximize yield from prototyping through signoff.
Design for Manufacturing / Design for Yield . Cadence solution for the advanced process node
Cadence has been collaborating continuously with leading library providers, integrated device manufacturers (IDMs), and silicon foundries to ensure realization of first-silicon success at 65nm and 45nm nodes. SoC Encounter GXL's design-for-manufacturing and design-for-yield technologies are validated and qualified by leading IDM customers and foundry reference flows.
NitinDeo,
Cadence Design Systems
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| | Encounter Track: Timing closure on a 1GHz DSP-processor using RTL Compiler and SoC Encounter
Timing closure has always been a major target for the digital implementation. In most designs SoC Encounter default optimization gives good results. In other high end designs additional advanced
techniques may be required. In this paper we will review the design and techniques used in SoC Encounter
to converge with timing / area.
NoamEshel,
Freescale Semiconductor
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| | SPB Track: Achieving efficient time to market with Cadence tools
Ethos Networks is a system startup company which set a goal to revolutionize the way Metro Carriers
think about Ethernet as simple and standard protocol for all multiple classes of services.
This session will focus on moving the company from architecture vision to fully operational platform while trying to reduce time to market.
The session will address the following:
- Basic understanding of Ethos 240Gbps cards and platform.
- From architecture to functional cards, using Concept and Allegro tools.
- Using Concept tool at electrical drawing phase and signal simulations.
- Describing Ethos cards and how Concept/Allegro tools incorporated at these goals.
- Using of electrical constrains to reduce time at layout phase.
- sing Specman Elite for verification and testing of Ethos new FPGA.
- Describing why choosing Specman integrated environment for debugging of a high speed
complex FPGA.
RafieGrinvald,
Ethos Networks
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| | SPB Track: Efficient Improve In Allegro PCB Editor Layout Time to Market by Using Custom Skill
Utility Programs.
Designing a complex electronics product is difficult and time consuming. Engineers use EDA and CAD tools to design and analyze products. These tools are essential to the process, but they only allow the engineer to automate a portion of their work. By developing custom application software designers
are able to apply user-assisted automation to the current manual process, and completing projects
substantially faster. Successfully Cadence Allegro PCB customization through the SKILL usage and
SKILL inter process with another programming languages (ActivePerl, VBA) will be present. This
customization integrated seamlessly into existing Allegro PCB environment and dramatically increases
users' productivity while significantly reducing time-to-market and time-to-profitability.
ShimonBeniaminovich,
Circuitec Ltd.
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| | Verification Track: eRM Enhanced with “Multi-Thread on Virtual Host” Method for Complex SoC Verification
This session suggests a new approach which uses E sequences (Threads) to emulate processors’
code. The processors run the threads while other simulation events occur, letting real scenarios take
place. Threads are written according to a methodology, which allow them to be run on any Host
and can be reused in all levels of design. At any point a virtual host can be replaced by a real model
that runs C code, if needed.
Advanced Verification of low power design using the common power format (CPF).
The industry's first complete solution integrates logic design, verification, and implementation
technology all enabled with the Si2 Common Power Format (CPF) to improve productivity,
reduce risk.
EranLahav,
Synergy Semiconductors
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| | Verification Track: Functional ECO with Conformal
Engineering Change Order (ECO) is commonly known as a manual process for fixing the existing logic implementation. In order to meet the tight schedule, the change is best to be limited to very small part of the design, such that the new change does not introduce other design issues, such as timing closure or clock skew. ECO can be classified into two categories: functional ECO and non-functional ECO (e.g., fixing timing violation). This paper focuses on the functional ECO and discusses an automated process to speedup the ECO changes. We will compare the results of automated vs. ECO done manually. The designer who performs functional ECO needs to change both the RTL and gate-level netlist to ensure function correctness. However, due to the logic synthesis optimization, the signal correspondence between RTL and gate-level netlist is hard to identify. In this paper, we would like to show how we can automate the ECO process in Intel. We present a technique based on the Cadence Conformal ECO that was used successfully at Intel. Conformal ECO provides user a solution to automate the functional ECO. First, the user first synthesizes the post-ECO RTL with the same synthesis script used previously in synthesizing the pre-ECO netlist. After the post-ECO netlist is synthesized, the Conformal ECO compare the pre-ECO netlist vs. post-ECO netlist. Using the command “analyze ECO” in Conformal ECO analyzes the minimal difference between two netlists (similar to output of the UNIX “diff “ command that called “patch”). Instead of storing the text difference in the patch file, the Conformal ECO patch file stores the logic difference and its boundary nets with a Verilog module. With the patch file applicable to the pre-ECO netlist, user can apply the patch on the pre-ECO netlist and make it functional equivalent to the post-ECO RTL.
ItaiYarom,
Intel Design Center, Jerusalem
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| | Verification Track: HW/SW Co-Simulation
Delivering an Embedded design to a customer goes hand in hand with delivering its software.
The HW-SW product must work efficiently together, be ready on time and with outstanding quality
without duplicating R&D effort. To achieve this extreme goal there is a need to check the SW-HW handshake using several platforms:
- HW Simulation (RTL model)
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SW simulation (SW model)
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Emulation
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post silicon
In this presentation a tool set and methodology allowing to achieve all of the above will be presented.
The presentation gives an example from Freescale’s new Multi core product, where RTL simulation, SW simulation (using Virtutech model) and emulation (using Palladium) is used.
AmitHermony,
Freescale SemiConductor
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| | Verification Track: SystemVerilog Open Verification Methodology (OVM) Technical Update
Cadence and Mentor Graphics recently announced that they are collaborating to create an open
source SystemVerilog Class Library and Methodology called the “Open Verification Methodology
(OVM)” that will be available later this year. OVM is a superset of Mentor’s AVM and Cadence’s URM
SystemVerilog testbench methodologies, and it will provide Verification IP interoperability with other
high level languages including e and SystemC. This presentation will give an overview of the OVM
SharonRosenberg,
Cadence Design Systems
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| | Verification Track: Translation of an Existing VMM-Based SystemVerilog Testbench to URM
Many features built into the SystemVerilog language make it ideal as a high-level verification language.
Using class libraries with SystemVerilog can take this a step further by enhancing productivity and
enabling better, more efficient reuse between engineers and between projects. The Verification
Methodology Manual (VMM) class library was one of the first SystemVerilog class libraries available,
and has been widely adopted. The Universal Reuse Methodology (URM) class library has more recently
become available, and while it is similar to VMM in many respects, there are also some important
differences. This session will describe the process of converting an existing testbench based on VMM
class libraries to one based on URM class libraries. It will highlight which aspects of the conversion
were straightforward and which aspects required more attention. The session will conclude by
summarizing the similarities and differences between the two approaches, and any potential advantages
achieved by doing the conversion.
KellyLarson,
Analog Devices
SharonRosenberg,
Cadence Design Systems
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