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| Download all files in this section | | | | | | | Adelante™ VD32040 Core and subsystem verification - What is verified where?
* Best Paper - Incisive Track
This presentation gives an overview of the verification methodologies used to verify a DSP, both core and sub-system. The device under verification is an embedded vector processor (Adelante™ VD32040). The VD32040 is developed within the DSP Innovation Center, which is part of Philips Semiconductors.
For the verification of the complete VD32040, various methodologies and verification environments are used. The challenge is the trade-off between minimizing the number of used methodologies and having a good verified product. The core itself is verified using the VD32040 simulator as a reference model. In this environment SpecMan is used for generation of a random DSP program, comparison of the internal registers (RTL vs. simulator) and implementation of functional coverage items. Most of the components in the VD32040 subsystem are verified using scoreboards written in ‘e’. This is done in an environment in which the VD32040 core is replaced by eVCs. Virtual sequences are used to generate corner-cases, e.g. transactions simultaneously valid on various interfaces.
All the test-benches developed during this project can be divided into five classes. These classes are: Block Level (CORE), CORE, Block Level (DSS), DSS and Core integration. Each class has its own reasons for existence. E.g. Block Level test-bench for larger components in the DSP subsystem (DSS) is mainly done to be able reach corner-cases more easily but also because neighboring components were still to be developed. During the presentation these reasons are explained in more detail.
Since verification closure is a very important topic for this project, a brief overview of the flow used in this project is given. This includes the usage of vManager for generation of a functional coverage report, using a verification plan (Word) as input.
Roger Witlox,
Philips Semiconductors
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| | Assertion-Based Formal Verification for STMicroelectronics' Nomadik™ Smart Video Accelerator
Formal property checking has been in use for a few years but the challenge of learning and mastering the formal property checking methodology has often been seen as an obstacle to adoption or has at least limited its use to a small community of expert users.
This paper describes how the STM Nomadik team successfully augmented their flow capabilities by adopting Assertion Based Verification (ABV) in general and formal static property verification in particular. The paper will provide an overview of the STM Nomadik sub-project which develops several key IPs on a low-power video platform. The participant will learn how STM's design team addressed complex verification challenges and how they were able to get the incremental benefits of using ABV at each step of the learning curve.
The first section will explain how the team decided to approach the PSL language and the impact of thinking in term of "properties" on their methodology and test plan definition. The use of dynamic assertion checking within the Incisive platform enabled the team to smoothly add assertion checking "on top" of their existing simulation based validation strategy as they were progressing on the learning curve.
The second section of this paper will show how static property checking naturally comes into place to enable early verification. The Nomadik team leveraged their investment in PSL-writing by using the Cadence Incisive Formal Verifier (IFV) tool to start validating their RTL prior to having any test bench. This paper will explain how IFV enables them to implement protocol checking in a fraction of the time required by more traditional dynamic approaches and will demonstrate that property checking can statically expose corner cases functional bugs that are difficult and sometimes impossible to detect with other verification techniques. The paper will also explain that static property checking provides a way to augment the design information available downstream in general and for verification steps in particular.
At this point of the session, participants will be exposed to the advantages of implementing an "assertion reuse" strategy to even further maximize their productivity.
Finally the paper will conclude with a discussion on how very early use of IFV can lead to a more efficient verification strategy. The session will illustrate these findings by Nomadik IFV experience on two critical IPs. Flow and methodology will be exposed, showing that IFV has been adopted smoothly as a complementary and powerful solution to STM's existing environment based on Specman co-simulation, and functional coverage
Francois Cloute,
STMicroelectronics
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| | DSP Sub-System - Spec to Closure
The SPEC to closure presents the verification process and flow of a sub-system from the ARCH spec stage, through methodology aspects, standalone environments and system-level verification.
It is highlighting the challenges in verification and presents a verification strategy to get to a test coverage of 100%.
Ran Snir,
CEVA, Inc.
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| | Extending a coverage driven verification environment with real software
HW/SW co-simulation is often carried out on complex chip level verification environments, executing software on the simulated target CPU or connecting an instruction set simulator to the hardware simulator.
In this presentation, we discuss the value of extending a coverage -driven subsystem or module level verification environment using real software. The software will be executed on the host computer and embedded into a layered hardware verification environment. The software raises the level of abstraction and saves work in implementing the stimuli generation part of the test bench. On the other hand the power of coverage- driven verification methodology will be applied to the software as well. This environment, consisting of a simulated hardware subsystem and the software, executed on the host computer, is simplest to debug.
Ernst Zwingenberger,
Micronas GmbH
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| | System Verification Techtorial
Leonard Drucker,
Cadence Design Systems, Inc.
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| | SystemC TLM for Complex IP's verification
This project illustrates the SystemC TLM-based verification flow in place today for IP in the context of a virtual SoC reuse methodology, allowing a smooth migration between levels of abstraction: Virtual SC TLM soc simulation, RTL co-simulation, RTL co-emulation, SoC simulation and SoC emulation.
For IP verification the strategy is to apply a test scenario with a transaction level testbench on a golden reference model to predict test signature, then replace it by the RTL while reusing transactional testbench and all tests. The same golden reference model is also used in a SystemC TLM virtual SoC for low level driver SW development before silicon and a subset of IP verification test scenarios are also reused by SoC verification to ensure design integration correctness.
Laurent Ducousso,
STMicroelectronics
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| | The TriCore advanced metrics driven Plan-to-Closure verification flow
Using the latest tools and methodologies, simulation based verification of most processors means generation and simulation of several billion instructions before first silicon is produced. It takes the best part of a calendar year to achieve this number. Compared to post silicon simulation where it takes less than a minute on a single piece of silicon to achieve the same. However bugs found after first silicon are both multiple times more directly expensive to fix (masks etc.) and indirectly because of the inherent delay to do a new silicon re-spin and time-to-market delay.
These quality and predictability risks increase at an accelerated rate. Exponentially growing design productivity leads to an ever growing design complexity which means that verification productivity must grow at the same rate to meet quality and timing constraints.
These challenges call for a scalable processor verification solution which will maximize the verification productivity. On a processor with a set of 200 instructions, 16 billion instructions will need to be executed to verify every 4-instruction combination. However, most bugs can not be found with this length of sequence. The challenge is to generate a limited number of longer sequences that have the highest possible probability of finding all bugs.
This presentation describes a solution to meet these challenges and mitigate the growing productivity, predictability and quality risks. The solution employs a Specman, eRM and sVM based Instruction Stream Generator (ISG) which is capable of doing Intelligent and Dynamic Weighted Random Generation which is reactive to an Instruction Set Simulator Model (ISS). In order to run as much high quality stimulus as possible a semi-automated regression environment was built which allows doing state of the art Metrics Driven Plan-to-closure Verification.
Pim Palmen,
Infineon Technologies
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| | Upfront test planning to make the best use of directed, constraint random and prototype verification environments
The paper talks about the challenges and strategies to verify a high performance multi processor system. The high-end System-on-Chip design consist of two complex FPGAs, the verification task was to prove correctness before SW integration on the platform started. To make the best use of the advantages of different verification strategies intensive test planning sessions were held upfront. The vPlan was used to identify the class and the focus of test cases. After grouping the verification tasks in directed, error, stress and electrical tests the verification environments were designed. The paper also shows how the right decisions in the assignment of tests to the verification environments helped to minimize the development effort of the test benches. In the conclusion the presentation will summaries the experiences of the verification management with the vManager and the different classes of bugs found with the chosen approach.
Jens Tiedemann,
Siemens AG
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| | Verification Planning and Tracking for a Multi-Company Project using Incisive Manager Subtitle: "Experience with a 13 Million Gates Automotive IC"
Verification planning and tracking is a crucial issue for multi-site/multi-company projects. For the previous mixed signal automotive ASIC project we introduced Cadence Incisive Manager to plan verification tasks, to start regression runs and to track the verification progress.
Verification planning using Incisive Manager looks different compared to conventional verification plans. While for conventional verification plans many details are included in one document the Incisive Manager approach plans verification on a feature base. Later in the planning and implementation phase each feature is assigned to a coverage item. These coverage items contain the details of the verification features. The main advantage of this approach is that the initial verification planning phase with many engineers involved is significantly shorter compared to writing a conventional verification plan. Additionally, for multi-site projects only the initial planning phase has to be done together, adding coverage items to features can be done at different locations later.
Efficient verification tracking for large ASIC projects is a challenging task. While in most projects many scripts are used to start the typical overnight regression runs we used a simple Incisive Manager configuration file to start daily regression runs. Incisive Manager was used together with the load balancing system SGE. The main advantage in this area is the easy way to configure regression runs and the reports generated from Incisive Manager. These reports show verification progress, failed and passed runs together with log files and the overall coverage.
Carsten Hoff,
ADIT
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