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| Download all files in this section | | | | | | | Accurate PLL Characterization Using Virtuoso Spectre RF Noise-Aware PLL Analysis
Phase locked loops are essential blocks in most analog/mixed-signal and RF applications today. They are used as frequency synthesizers and polar modulators in wireless applications. Because of the complexity of PLLs, the different time constants involved (two widely-spaced time constants), and the fact that the voltage-controlled oscillator (VCO) frequency often oscillates several orders of magnitude faster than the reference frequency, simulating PLLs at a transistor level presents multiple challenges and is extremely time consuming. Several approaches are available today using FastSPICE simulation, behavioral modeling, or stochastic analysis. FastSPICE simulators, by speeding up PLL simulation time, enable designers to characterize the PLL dynamics such as locking and settling time. Behavioral model-based simulation approaches allow designers to trade off the various blocks characteristics and PLL performance by accelerating simulation speed. However, none of these approaches provides a successful noise analysis of the complete loop. Virtuoso Spectre RF recently introduced a new flow aiming to provide this capability. This flow includes a new model formulation for the VCO that predicts its dynamic behavior. It uses a non-linear model and can capture the dynamics of oscillators due to VCO pulling, including injection locking and power-supply interference. In addition, the VCO model is automatically extracted from transistor-level netlist, eliminating the need for additional calibration. This paper presents the Spectre RF noise-aware PLL flow within the Cadence environment and explores its strengths versus other existing flows. Several Integer-N PLL testbenches, including phase frequency detector (PFD), charge pump (CP), VCO, and divider, serve as experimental vehicles to validate the Spectre RF flow. The first section of the paper develops Spectre RF noise-aware PLL flow theory and use model. Section two presents the advantages of this flow over other approaches. Section three presents the experimental results.
Helene Thibieroz,
Cadence Design Systems
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| | An Analog/Mixed-Signal IP Development Flow
Design effectiveness, quality, and reuse are hot topics in analog/mixed-signal IC design, but the design style has not changed significantly over the last 20 years— it is still more manual, relying heavily on designer experience and well-established pure simulation tools. In the past, both reuse and design optimization tools received many prejudices in the design community and have been applied successfully only in a few areas. To solve these difficulties, a combined flexible environment is presented that is based equally on tools, reuse techniques, and best practises. Especially the last area is often overlooked, but contributes highly to successful application. Our flow is based on the Cadence Virtuoso Spec-Driven Environment and the modeling and characterization plug-in, which allows a high degree of flow automation, i.e. it can generate testbenches and models based on class-specific templates using an easy-to-learn programming language openDCM. Improvements to this base flow will be presented, including an underlying IP library featuring more than 300 circuits covering practically any kind of AMS block. The key is bringing software and design knowledge together and smoothly enhancing the usual design style. The work covers 10 years of design experiences, and our observation is that the major benefit is in always having something that works by built-in, best-practise, state-of-the-art examples. Also, IP reuse is not only beneficial for pure circuit or layout reuse, but also for specifications, modeling, and testbenches. Clearly, such improvements are hard to benchmark. Not only does design speed matter, but also correctness, quality, and documentation.
Stephan Weber,
Cadence Design Systems
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| | An Innovative Verification Flow for Mixed-Signal SoC Validation
Since the latest sub-micron technologies enable designers to mix digital/analog/RF IPs in a single chip, mixed-signal verification at the top level has become a challenge. The complexity of validating such designs highlighted the necessity of running efficient mixed-signal simulations and underlined the lack of appropriate methodology in the domain. This paper will present how a mixed digital/analog/RF SoC can be validated at different abstraction levels (from high-level to transistor-level modeling), using a common design database and a single verification language. Techniques inherited from the digital world have been adapted to the analog environment to minimize testbench development time while maximizing functional coverage. The example of a Specman simulation of a digital sinus generator interfacing a DAC at 1GHz will be detailed. Having a single unified and automated simulation environment during all design steps has significantly improved validation productivity and efficiency: duplication effort between digital and analog teams was reduced to zero and functional coverage was clearly reported for analog IPs, guaranteeing a higher quality of verification.
Luis Rolindez,
STMicroelectronics
B. Foret,
STMicroelectronics
C. Adobati S. Engels,
STMicroelectronics
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| | An Innovative Way to Include Bond Wires in the Design Flow
Despite the emergence of new microwave interconnect technologies (bumps, thin vias), conventional wire bonding remains the dominant low-cost, high-reliability, high-manufacturability chip connection technology. In this paper, we will present how we use Virtuoso Layout Editor to have a 3D graphical representation of bond wire arrays. This new interface developed with SKILL language is completely integrated with our design flow. DRC and LVS checks combined with electrical simulations of the whole application become easier. This innovative method helps designers to define in minutes something that previously asked for more than three hours.
Hubert Furdyna,
NXP Semiconductors
Magali Aubrey,
NXP Semiconductors
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| | Automated Creation of a Customized PDK for 90nm
The goal was to create a PDK that enabled a number of methodologies at CSR that were not available in the standard PDK. In addition, some undesirable features of the PDK needed to be disabled. As much of the existing PDK as possible was reused to minimize the cost of development. This included building wrapper Pcells around the standard Pcells to enhance their behaviour to match the CSR methodology. Also, various techniques were used to ensure that the integrity of the design was maintained at all times. For example, avoidance of CDF callbacks for derived data. This work was done in partnership with Cadence, using SKILL to automate the process. This will be illustrated with a discussion of how the approach was used to build a 90nm RF front-to-back PDK. The main benefit of such an approach has been speedy adoption of Cadence tools. Much of the development work was used to build a 65nm PDK in less than a week. Incremental updates to the 90nm PDK from the foundry partner can also be incorporated very rapidly.
Fabian Giroud,
Cambridge Silicon Radio Ltd
Andrew Beckett,
Cadence Design Systems
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| | CDB to OA - The Migration Report
austriamicrosystems has migrated its well-recognized and well-established Process Design Kit, the HIT-Kit, based on Cadence software to the OpenAccess database and the Cadence Virtuoso platform 6.1. Migration of library data, Pcells, technology files, and skill routines brought up a number of issues such as the connectivity model used for Pcells, specification of vias in the technology files for different tools, and problems with the usage of the new streaming functionality. This presentation will give an overview of the migration procedure including data validation, translation to the OpenAccess standard, and final verification of the translated data. Further, it will give detailed information about the challenges and pitfalls faced during migration and the in-depth cooperation with Cadence to finally end up with a qualified HIT-Kit for Cadence 6.1 and OpenAccess.
Gernot Heiling,
austriamicrosystems
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| | Current-Flow-Aware Physical Design and Verification of Complex High-Power Automotive IC Designs
The correct consideration of current flow effects within complex IC metallization patterns is essential to avoid problems due to electromigration (EM), electrical overstress (EOS), and IR drop in the final silicon. In contrast to previous presentations of signal and power line electromigration and IR drop issues in digital ICs, this presentation focuses on related design and verification challenges for custom-built high-power IC designs. The challenges for physical design and verification comprise (1) circuit simulation to obtain adequate terminal current values, (2) the correct current-flow-related ESD protection design, (3) the current-flow-aware routing of nets, (4) current-flow-aware layout compaction, and (5) the electromigration lifetime assessment of arbitrary layout structures. Possible solutions and design approaches will be provided for arbitrary terminal currents and arbitrary layout structures. Several case studies from real automotive IC designs will be discussed to show the practical relevance of the topic as well as to underline the need for commercial support and consideration of the mentioned design problems within EDA tools. The presentation concludes with a summary of "lessons learned" and specific feature requirements for future custom IC design tools.
Goeran Jerke,
Robert Bosch GmbH
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| | Design Challenges of Large Mixed-Signal ASICs with Hierarchical Segmentation.
When designing mixed-signal ASICs with a large number of regular and repetitive structures, it is necessary to create a complex hierarchy of cells. Often, the interfaces between analog and digital circuits are situated at low levels and both analog and digital signals cross several levels of hierarchy. Thus, it is hard to find a methodology that can handle AMS simulation, floorplanning, full custom analog layout, digital place-and-route, parasitic extraction, timing analysis, and chip assembly in one flow. A field programmable analog array (FPAA) is presented, which features a digitally programmable time-continuous analog filter consisting of approximately 50,000 analog transistors and digital configuration circuitry in a 130nm technology. A complete design flow using Cadence software is presented, showing challenges and solutions, which lead to a successful manufacturing of the presented FPAA.
Joachim Becker,
IMTEK, University Freiburg
Prof. Dr. Yiannos Manoli,
IMTEK, University Freiburg
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| | Envelop and Fast Envelop Simulations for RF/AMS Design Challenges at 90nm and Below
One of the biggest RF/AMS design challenges is the presence in the same IC of more and higher frequencies with different types of lower frequency modulations. In RF applications, the difference between carrier frequencies and baseband frequencies can be huge: 1,000 or more. The transient simulations have more and more difficulties, and bigger frequency differences, to tackle in a decent simulation time. One of the best possibilities is to use envelop simulations with one of these three Virtuoso simulators: Spectre RF, UltraSim, or AMS Designer. In this presentation, both learning curve test cases and real pilot circuits at 90nm and below will be evaluated using envelop algorithms: receiver, transceiver, ADC, etc. The final objective is to help the designer choose the best envelop algorithm and tools to decrease simulation time and accelerate time to market for these IC designs.
Dr. Didier Depreeuw,
NXP semiconductors
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| | Inductor Design Flow
Within the inductor design flow, planar on-chip spiral inductors as well as transformers can be designed on demand by an IC designer. The flow allows creating an inductor/transformer layout, a medium quality equivalent circuit within minutes, and a high-quality model. The model applied depends on how important the device is in the circuit. The on-demand created models and layouts are LVS and DRC clean. To quickly create and optimize the inductor/transformer, the Cadence Virtuoso Passive Component Modeler's quasi-static approach is used. For a precise solution, a full-wave electromagnetic solver can be applied. The inductor design flow has been applied in several successful VCO designs to create symmetrical and asymmetrical inductors. Using the flow, a new first-time-right device is created. There is no need for an inductor library in any technology. The device occupies the minimum available chip area and is always suited to the application and technology.
Dr. Krzysztof Kitlinski,
Infineon Technologies AG
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| | System-on-Chip Development: How to Put a Methodology into Practice
The only way to achieve the productivity necessary to meet today's time-to-market challenges is to reuse and leverage existing IPs and design modules using a proprietary design platform like SITaR. SITaR stands for "Submit, Integrate, Test, and Release" and is a simple workflow that can be used for any kind of design like (hardware, software design, or combined development). SITaR is applicable when a design consists of multiple blocks submitted by multiple contributors. It is based on the notion that there are two distinct roles - a designer and an integrator - in a project. The fundamental notion is that ALL changes to a design are made against a qualified and stable baseline. The ENOVIA MatrixOne Developer Suite supports the capability of working in a truly "modular" fashion using a feature called Hierarchical Configuration Manager (HCM). Working with HCM is well suited to the block/modular needs of HW/SW designers as well as providing the following capabilities: · Block-level abstraction of data representation · Hierarchical representation of design · Formal (hierarchical) release mechanism · Simple methodologies for re-use of blocks across projects · Issue and email subscription through hierarchy, allowing block dependencies to be more easily managed. The SITaR package takes these capabilities and wraps an out-of-the-box use model; hence, with SITaR installed in an SoC Developer Suite, the system will adopt a methodology that is both quite formal in nature, yet very simple and logical to use. SITaR is a process formalizing the development and integration of design blocks (modules) into a design. Those blocks can be hardware, software, or mixed in nature, and their actual data types are not limited. Multiple, parallel development and submit flows can all channel into a single flow. This convergence of parallel to serial activity is managed through the definition of user roles.
Felix Benjamine,
ENOVIA Matrix One
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| | Use of the Incremental Technology Database for Design in IC 6.1 and OA 2.2
The OpenAccess (OA) 2.2 technology database promises to cut the support required to maintain tech data for multiple tools in the design flow. Along those lines, the incremental technology database (ITDB) was introduced in IC 6.1.0 and OA 2.2. The ITDB allows the tech data to be stored in multiple libraries, minimizing rule duplication across multiple variants in a process node. This is a new capability we did not have in CDB and is very powerful, but it can introduce complexities as the technology data is partitioned. We will give a short introduction to the ITDB and look at some of the recommended implementation practices for partitioning and binding technology libraries. We will address some of the interoperability concerns with other OA-based tools such as the Cadence Space-Based Router and SoC Encounter system. This best-practices paper will help CAD groups, library developers, and designers implement the ITDB in a manner that supports their design style while minimizing confusion and problems.
Ted Paone,
Cadence Design Systems
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