| | | | | | Achieving a high level of integration using the Cadence RFIC Flow
Siano, an Israeli start-up company supplies a solution for multi standard MDTV reception. Siano is a key player in the emerging MDTV market, and the only company today with a solution that supports both the DVBH standard and T-DMB standard with a single chip solution. This solution is combined of an RF tuner chip and a Baseband demodulator chip packaged together in a SIP package.
Meeting MDTV standard requirements requires a design flow that enables a high level of simulations at all levels starting from design partitioning down to transistor level simulations after layout extraction. The following presentation describes this flow and how it was implemented on the sms1001 RF chip.
NeilFeldman,
Siano
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| | Building the right methodology with AMS methodology kit
During the past 2 years, PowerDsine's VLSI team was upgraded to become a Silicon Design Center with real Analog and Mixed Signal design capabilities. The Cadence AMS Methodology Kit was proven to be highly effective when building up the "right" methodology for Mixed Signal Structures. This Kit was used by PowerDsine's team to study and practice the full front end design flow for mixed signal ICs. The Kit includes real and practical analog circuits, verilog code, behavioral models and test benches, and a typical PDK enabling our VLSI engineers to gain the confidence and build up the necessary experience in about 1 week. Using VerilogA, Spectre & AMS for mixed level and mixed mode simulations of RTL, Verilog-A Models and schematics, while exercising in a "clean" data base like a "school reference model" - our engineers got the necessary practice to begin doing full system design.
NadavBarnea,
Powerdsine
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| | Cadence Conformal LEC The Intel Experience
Formal verification in general and logic equivalent checking in particular are problems that are hard to solve. However, most of the hardware logic don't fall in the worse case category and therefore can be computed by logic equivalence checking tools like Cadence Conformal (LEC). In this presentation we will explore how to use the Cadence Conformal LEC tool capabilities to verify different types of designs. In particular, we focus on the Conformal Ultra capability for verifying complex data-path synthesis and layout. We use it together with the set effort "complete" command, in order to force the Cadence Conformal LEC to compare all the aborted state points. The design we present is a 1 Gigabit Ethernet chip with around 10 million standard cells. At first look we thought that we would need to use the divide and conquer technique and split the big design into smaller blocks in order to complete the verification. To our surprise, using the Conformal Ultra together with the effort "complete" we managed to verify the entire design in one flat run. In this presentation we discuss when to use the different Cadence Conformal LEC capabilities and what benefits they provide. When to use the Conformal Ultra and when not? Why you need to use the effort complete wisely? The following learnings are based on using the Cadence Conformal LEC on different types of designs at Intel. This kind of information can provide a significant saving of time and increase the user productivity. We wrap up by presenting additional tips of accelerating the design flow using the Cadence Conformal LEC.
ItaiYarom,
Intel
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| | Encounter and PVS in CGX5900 chip implementation
In this paper we will explore the SOC Encounter product (First Encounter, NanoRoute Ultra, CeltIC-NDC) and Cadence new Physical Verification System (PVS) to implement netlist to GDS2 flow based on the experience in Avnet Semiconductor Israel. The flow is implemented in Avnet on a CGX5900 chip designed by Cell Guide. CellGuide will present CGX5900 design features and then Avnet will go over Encounter and PVS scripts, intermediate results and experience with the tools.
ArieKomanitzky,
Avnet Asic
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| | Enterprise System Level (ESL) Verification
Recognizing the role that software and firmware play in modern SoC designs, there is a need to address System Level solution at the Enterprise level. ESL verification is the most critcial task in this domain. For long time, there was a major fragmentation in this market segment. Cadence has introduced its new Enterprise System Level (ESL) Verification solution in December 2006 addressing multiple levels of abstraction and multiple specialists with a single verification environment. Ran Avinun, explained in this presentation the problem and the details of the Cadence solution.
RanAvinun,
Cadence Design Systems, Inc.
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| | Hardware Emulation of the MPC83xx product family
In this presentation we present the emulation methodology that was developed for the 83xx family desings and applied successfully to meet our verification goals.
Cadence PDII emulation solution was/is used for executing of good sample set of data frames and software commands as key to archiving very high confidence silicon.
DavidKaushinsky,
Freescale
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| | Implementing a constrained random testbench environment including coverage using System Verilog
This session discusses the implementation of SystemVerilog to create an efficient and generic verification environment. Constrained randomization aided by macros was used to generate stimulus, SystemVerilog assertions (SVA) were used to verify protocol and contribute to coverage, and covergroups were used to measure the functional coverage.
GuyHorovitz,
Saifun
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| | Incisive Formal verification
In this work we show how we used formal tools to effectively verify a complex multiple clock domain AXI arbiter. These tools consist of automatic checks and user defined checks. The arbiter had approximately 20, 000 flip-flops. Running the tools on this size cannot be expected to be effective. We show how an effective flow was defined and executed in order to take advantage of the formal tools given this components size. We analyze the advantages and disadvantages of such a flow.
HillelMiller,
Freescale
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| | Virtuoso Custom design Platform
This presentation provides an Introduction to Virtuoso 6.1
AndrewBeckett,
Cadence Design Systems, Inc.
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| | VSDE for analog development and verification
Transchip VSDE for analog development and verification Modern process suffers from wide distribution on the parameters of the transistors and the parasitic impedances. Analog development for low power, low power and high frequency is required for modern chips. The flow usually includes testing environment development, initial design, optimization, testing and full validation.
The longest and hardest steps are the optimization and validation. The flow for analog optimization is long and can take high effort, so needs to be as automated as possible. Verification and full coverage across all process/voltages/temperature is also long and time consuming. The Virtuoso Aptivia Specification Driven Environment, fully integrated from the beginning of the development process, can help reduce complete development time from weeks to days.
RoniEl-Bahar,
Transchip
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