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 | |  | | | | | CDN User's Group Interview on DDR2 with Randy Wolff
Randy Wolff
Micron Technology, Inc. | |
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1) How is designing-in DDR2 different than DDR & other memory interfaces?
Progressing from one memory technology to the next always presents new Signal Integrity issues to deal with related to higher operating frequencies, new package styles, and tighter timing relationships between signals. DDR2 Memory system design has presented unique challenges to our Micron simulation team since we first began working with it about 4 years ago. Two technological advances in particular have presented the most challenges. The first is the addition of resistive termination on the memory die for Data signals, effectively moving the bus termination off of the motherboard. This technology, known as On-die Termination (ODT), can drastically improve signal integrity, but it also makes system level simulation increasingly complex. ODT has 3 settings: 50 ohms, 75 ohms, and 150 ohms and may be found on the memory controller as well. When multiple ranks of memory devices share the same bus, you can end up with a very large number of possible termination schemes to analyze for all READ/WRITE cycle combinations. Also, simulation time may be wasted if invalid termination schemes are automatically analyzed by the simulation software. The second challenge arises from setup and hold timing analysis. In addition to timing analyzed at specific voltage thresholds, DDR2 timing analysis accounts for slew rate effects on the memory device’s input receivers. To properly measure setup and hold timing, slew rates must be measured on every signal, and then a lookup table must be used to find the additional timing effect. This process, known commonly as slew rate derating, is very tedious and time consuming if done manually through a waveform viewer interface. Other minor differences exist in measurement of signal overshoot through area instead of finite voltage limits and in measurement of eye diagram aperture at combinations of AC and DC voltage thresholds. Complete analysis of a DDR2 system can be very time consuming, so the more EDA software can do to automatically analyze SI waveforms and timing, the faster and more accurate our simulations will be.
2) What is Micron doing to shorten customers' time to design-in DDR2 memory interfaces?
Micron is committed to helping our customers successfully design-in DDR2 memory. Besides writing application notes explaining the technology and working with customers directly to help solve design issues, we also work closely with many EDA software vendors. Working with EDA vendors is a win-win for Micron, our customers, and the EDA software companies. The close relationship we have with Cadence allows us to easily communicate tool enhancements needed to simplify simulations of new memory technologies. Participating in development of the DDR2 Design-in IP Portfolio has led to software enhancements that will help all of us simulate DDR2 designs in less time as well as a clear path for our customers working on their first DDR2 designs to follow.
3) Why did you choose to work with Cadence?
Cadence and Micron have fostered a very positive relationship over the years. Micron's DIMM products are designed using Cadence software, and many designs are simulated with Cadence software. Working with Cadence to create the DDR2 Design-in IP Portfolio helped ensure we were supporting our mutual customers better. Cadence’s broad customer base also means that many customers will benefit from our efforts.
4) What is the major benefit joint customers will see from the DDR2 design-in IP portfolio that was just released?
The biggest benefit customers will see is an easy to follow design methodology that will help them learn the DDR2 technology and be successful in their design projects. The portfolio allows for rapid exploration of signal integrity and timing concepts complete with ready to use topologies and fully setup simulation environments. Scripting included with the portfolio aids customers in slew rate derating, and the 15.7 release of Cadence PCB SI includes a new feature, Bus Simulation, to aid in analyzing termination schemes properly. I hope that customers using the portfolio will spend less time designing their first DDR2 memory interface.
Find out more about the Cadence DDR2 Memory Design-in IP
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