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 | |  | | | | | Cadence interviews Dr. Sogo Hsu for his comments on the design-in IP for DDR2 memory interfaces announced this week by Cadence
Dr. Sogo Hsu
Foxconn Inc. | |
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Q. What are your impressions of the design-in IP for DDR2 interfaces that Cadence, Altera and Micron have introduced this week?
Note: read the prior interview with Dr. Hsu "Challenges for Designing with DDR2"
A. We are working closely with Cadence to develop solutions that will allow designers to characterize the DDR2 interface, until now, this type of complete design-in IP has been impossible as memory module/controller vendors were required to develop customized tools. This new DDR2 design-in IP is a great step towards a common signal integrity analysis tool for system designers, memory vendors, and the industry at large.
Allegro DDR2 design-in IP is the most complete solution on the market with closely integrated constraint-driven design flow and post-routing simulation, shortening design validation cycle time for designs with DDR2 interfaces. This new design-in IP also helps designers ensure that timing and voltage margins are met for JEDEC specifications before PCBA stage.
Q. What do you think will help system designers most in dealing with the challenges of designing in DDR2 memory interfaces?
A. The DDR2 design-in IP is very easy to use. In the past, we have to pay attentions on configuring different ODT setting, PCB routing parameter and probing position (on pads or on die). In addition, write cycle and read cycle is different in DQS/DQ edge alignment mechanism. We have to take different timing scenarios during simulation configuration setting. Using DDR2 design-in IP, we are able to setup these parameters in short time. Later on, take a coffee break and wait for post-routing simulation results in couple of minutes.
Q. How is working with DDR2 Design-in IP portfolio different than users working with Micron and Altera directly?
A. To make sure the simulation results are believable and reliable is very important in design stage by using simulation strategy. In DDR2 interface simulation chain; there are several bottlenecks easy to be incorrect setting. Simulations without validation may well be more dangerous than no simulations at all in some cases. Working with DDR2 design-in IP is able to reduce the risk of incorrect simulation result. Especially, we can still achieve high-quality simulation results even the job is able to move forward to junior level of engineer.
Q. How would adding other memory vendors be valuable to Foxconn?
A. First of all, I have to express my sincere thanks to memory vendors, especially, Micron and Altera. Getting professional technical supports from vendors, such as component models and DIMM board layout, is the key factor to achieve successful system design with DDR2 signals in short time. Without this kind of technical support, it was difficult to clarify the ownership of memory compliant issue and fell in a try-and-error iteration. As a major system house, Foxconn looks forward to seeing more memory vendors to provide deeper design files to customers, as well as join DDR2 design-in IP program. These kinds of support are helpful to shorten the design validation cycle in system design. Accordingly, speeds up the time to market. System houses and memory module vendors will get win-win relationship in this working model.
View presentation by Dr. Hsu from the 2006 Silicon-Package-Board Design Seminar in Taiwan, "An Indispensable Partnership"
Find out more about the Cadence DDR2 Memory Design-in IP
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DDR2 design-in IP for memory interfaces announced by Cadence, Dr. Sogo Hsu comments
About the author
Sogo Hsu is an electrical engineering leader at Taipei Design Center, Foxconn Inc., where his team works with several board design teams that are responsible for all aspects of electronic design of high-speed digital and high-frequency products. He received a Ph.D. from National Taiwan University, Taipei, Taiwan in 1995, and joined Foxconn in 2002 to lead electrical simulation team. The responsibilities for this team include providing design guideline in development stage and ensuring electrical quality before PCBA. He is interested in topics including high speed digital design flow automation, signal/power integrity simulation, timing verification, noise suppression methodology between power/ground plane structure, and interconnection modeling for packaging. |
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