Thursday, July 29, 2010     Register | Login | Search | Contact Us
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
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Functional Verification
Forum Name Topics Replies Last Post
What issues are you facing using acceleration and emulation? Forum moderator: Tom Paulson 55 62 This forum is now read on...
by host
8/02/2008 9:05 AM
A place to share ABV and formal analysis questions, answers, and commentary. Forum moderator: Ross Weber 56 155 This forum is now read on...
by host
8/02/2008 9:07 AM
What challenges do you face in using the SystemVerilog language for design and testbench development, assertions and IP re-use? Forum moderator: Nitin Sharma 201 682 This forum is now read on...
by host
8/02/2008 9:09 AM
How does verification planning, or lack of, impact your designs? Forum moderators: Stylianos Diamantidis; Akiva Michelson 29 41 This forum is now read on...
by host
8/02/2008 9:13 AM
How are you using e language for testbench development and IP re-use? Forum moderator: Joseph Hanli Zhang 74 197 This forum is now read on...
by host
8/02/2008 9:16 AM
Upload your e Files here. Give a brief summary of how to use the code. Forum moderator: Stylianos Diamantidis 37 39 This forum is now read on...
by host
8/02/2008 9:18 AM
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