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Low power
Designing for Low Power involves tradeoffs. How are you handling these decisions?
Forum Moderator:
Chris Byham
44
41
Visit the new Cadence Com...
by host
7/13/2008 4:02 PM
Design Data Management
Design Data Management challenges increase with multiple sites and multiple teams. Let’s develop best practices for IC design management.
Forum Moderators:
Britta Krueger, Chris Goldstein, and Rick Stanton
7
14
How to generate hierarchi...
by julian2007
7/15/2008 2:01 AM
Statistics:
Total Forums:40
Total Topics:2633
Total Posts:8801
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Layer Specific Routing information
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Layer Specific Routing information
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Layer Specific Routing information
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Special Topics
--Low power
--Design Data Management
Digital IC
--Synthesis and test
--Formal verification
--Floorplanning, Place and route
Custom IC
-- Custom IC Electrical Design
-- Custom IC Physical Design
--Shared code - SKILL
Silicon-package-board
--Signal Integrity and Modeling
--PCB Design
-- IC Package, SiP and Co-design
--Shared code - SKILL
Functional Verification
--Simulation, Acceleration, Emulation
--Assertion-Based Verification and Formal Analysis
--SystemVerilog
--Verification Planning
--<i>e</i>
--Shared code - <i>e</i> Files
Cadence Academic Network
--AMS Methodology
--RF Methodology
--Verification Methodology
--Cadence Academic Network Member List
--Cadence Academic Network Announcements
--Cadence Academic Network Event Notices
--Cadence Academic Network General Questions
General topics
--Suggestions
--Event Notices
--Jobs
ActiveForums 3.6
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