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Subject: .subckt model in Sigxp
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imsong
Posts: 18
Online: User is Offline
3/17/2006 4:05 PM  

Using dml by PackagedDevice with Espice syntax in Sigxp, I am facing error message in tlsim.log like this "ABORT: Syntax error in expression source parser: Missing expression".
My circuit is above
("via.dml"
 (PackagedDevice
  (fsb_via_pth_bdg
   (ESpice ".SUBCKT fsb_via_pth_bdg 1 2 3 4 5
C001 4 3 8.78774E-013
V001 1 5 DC 0
L001 5 6 2.30274E-010
R001 6 4 0.015179
V002 4 7 DC 0
L002 7 8 2.30274E-010
R002 8 2 0.015179

C101 8 3 8.78774E-013
V101 4 10 DC 0
L101 10 12 2.30274E-010
R101 12 8 0.015179
V102 8 14 DC 0
L102 14 16 2.30274E-010
R102 16 5 0.015179

*ADDED
K001 L101 L102 0.2
F001 16 5 V102 0.2

.ENDS fsb_via_pth_bdg" )
   (PinConnections
    (1 2 )
    (1 3 )
    (2 1 )
    (2 3 )
    (3 1 )
    (3 2 ) ) ) )
 (LibraryVersion 136.2 ) )

"*ADDED" part is inserted for testing simulation in SigXP.
But I think inductance coupling and dependant source are not available in this PackagedDevice.
I can't use Kxxx and Fxxx in SigXP. Is that right?

imsong
Posts: 18
Online: User is Offline
3/17/2006 4:09 PM  
 (ESpice ".SUBCKT fsb_via_pth_bdg 1 2 3 4 5
=>  (ESpice ".SUBCKT fsb_via_pth_bdg 1 2 3
After that SigXP run, but Fxxx is  not likely support, right?
lwang
Posts: 0
Online: User is Offline
3/20/2006 6:42 AM  
Which version are you using?
Donald Telian
Posts: 42
Online: User is Offline
4/03/2006 1:48 PM  

Both Fxxx and Kxxx are supported in Espice, but the syntax differs from what you show.  Refer to the Espice Syntax Manual accessed under Help for the proper syntax.   Donald


Donald Telian
SI Consultant
telian@sti.net
559-760-5793
imsong
Posts: 18
Online: User is Offline
5/15/2006 6:40 PM  
Posted By imsong on 5/15/2006 6:39 PM

Version 15.2



jbhorner
Posts: 4
Online: User is Offline
5/16/2006 6:30 AM  
In releases 15.5 and beyond, the more standard form of the controlled sources is also supported. In 15.2, you will need to format it as follows.
F012L012 20 10 V012 0.25 <<<< HSpice syntax

...meaning that 25% of the current in V012 should appear between nodes 20 and
10. Allegro PCB SI would want it to look like:

F012L012 20 10 i='0.25*i(V012)'

imsong
Posts: 18
Online: User is Offline
12/05/2006 9:04 PM  
Allegro SI 15.7
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