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Subject: Simulating with AC Coupling
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aball
Posts: 7
Online: User is Offline
6/08/2006 11:35 AM  
Can anyone advise a SigNoise novice the best way to simulate multi-gig signals which are AC coupled ? The problem I have is that if I run at the resolution I need to examine the signals at, it takes an age for the caps to charge so that the signal levels are within the normal operating range. Ideally I either want to be able to simulate very coarsely for a period, then change the res, or perhaps I could force the initial voltage on the caps somehow ? Cant do any of this manually (per simulation), as I have a LOT of such signals to sim in batch mode. I would prefer not to modify either the design or the device models if possible


Please forgive if this is a dumb question, or the answer is blindingly obvious (or both) !
Kalevi2
Moderator
Posts: 69
Online: User is Offline
6/09/2006 4:42 AM  

Aball:

The answer is not blindingly obvious and without major study of the Cadence spice user docs, you could not figure it out. Fortunately Cadence has provided the answer:

From SourceLink if you search for capacitor initial conditions-

The the reason this is happening is that the initial DC voltage across the capacitor
is not the voltage that would be there if the circuit had been switching for a long
time, the time=0 value has the circuit in a steady state, and then it starts
switching for time > 0.

The initial voltage across the capacitor can be set by modifying the ESpiceDevice model
for the capacitor. For example this model will set the initial capacitor voltage to
be 0.92 volts.


("cap_with_initial_condition.dml"
(LibraryVersion 136.2 )
(PackagedDevice
(cap_with_initial_condition
(ESpice ".subckt cap_with_initial_condition 1 2
C1 1 2 10000p
g1 1 2 i='if (time <=0) (1e3 * (v(1,2)- 0.920)) else (0)'
.ends cap_with_initial_condition
" )
(Manufacturer Signetics )
(PinConnections
(1 2 )
(2 1 ) ) ) ) )
Kai Keskinen
aball
Posts: 7
Online: User is Offline
6/10/2006 12:11 AM  
Kai

Thanks !
As ever, SourceLink is great IF you know exactly what to search for
Seems a pity there's no way the simulator can automatically do this sort of initialisation based on the actual circuit i.e. accounting for the high/low driver output levels and assuming average 50:50 mark-space

Alan
Donald Telian
Posts: 42
Online: User is Offline
6/13/2006 12:58 PM  
Alan,

Often the sim results are the same with and without the cap.  Let us know if that is true in your case.  If it is, you can just leave its parasitics there (ESL, ESR), remove the C, and save a lot of time/hassle.

Donald
Donald Telian
SI Consultant
telian@sti.net
559-760-5793
Kalevi2
Moderator
Posts: 69
Online: User is Offline
6/14/2006 5:16 AM  
Donald has a good point. Messing around with initial conditions can be really time consuming. It is better to remove the cap and just add the parasitics. Do an analysis on the lowest frequency your data rate and encoding will create and make sure the capacitor value is large enough to not cause any issues.
Kai Keskinen
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