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Forums > Silicon-package-board > Signal Integrity and Modeling

Subject: Should I worry about die signal overshoot?
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fitzdean
Posts: 5
Online: User is Offline
6/16/2006 3:11 PM  
I have a SigXplorer simulation showing overshoot at the die level for a mobile DDR (1.8V) device driven by a fairly new ARM11 device that violates the overshoot specification fr the memory.  However, the package pin shows no specific overshoot problem.  The trace length is less than 1/2 inch and the speed is 133MHz.  The trace is controlled impedance.  According to the memory vendor, they say their specification is for the waveform at the package pin.  But according to the CPU vendor and a high speed design consultant, they say that the signal performance at the die is also important.

So, who do I believe?

The simulation only fails the overshoot specification when the Simulation Modes is set to FTS Mode: Fast.  Typical and slow are fine.  Attached is the printout from the simulation.  Feel free
to email me if you have a definitive answer.  Thanks in advance.

Attachment: fast_plot.pdf
Kalevi2
Moderator
Posts: 69
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6/19/2006 8:39 AM  
One thing to keep in mind is that the fast case is VccTypical+10%. If you take the magnitude of the overshoot and subtract from it the fast case Vcc and then add the typical case Vcc, do you still exceed the spec? What kind of package model do you have on this device?
Kai Keskinen
Kalevi2
Moderator
Posts: 69
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6/19/2006 8:43 AM  
Signal performance at the die is the important thing since that is what the silicon sees. Since we cannot use a scope probe to access the die, timing numbers are referenced to the pin except rarely when you are provided detailed package delays.
Kai Keskinen
fitzdean
Posts: 5
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6/20/2006 8:23 AM  
Yes, the simulation still would show violation if I subtracted off the 10% high on the VCC.
Kalevi2
Moderator
Posts: 69
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6/20/2006 8:31 AM  
What kind of package model do you have?
Kai Keskinen
fitzdean
Posts: 5
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6/20/2006 10:42 AM  
137 pin FBGA, 0.8mm pitch, stacked DDR/NAND, not sharing data bus.
Kalevi2
Moderator
Posts: 69
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6/20/2006 11:17 AM  
What kind of package model do you have?
Kai Keskinen
fitzdean
Posts: 5
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6/20/2006 2:42 PM  
how can I tell?  All I have is the IBIS model the memory vendor sent.
Kalevi2
Moderator
Posts: 69
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6/21/2006 3:55 AM  
Dean:

You can tell by looking at the IBIS model. Is there only 1 set of package RLC with typ, min, and max at the top of the pin list or are there pin specific RLCs (unique per pin) or is there a distributed or sparse matrix package model at the end of the ibis file?
Kai Keskinen
fitzdean
Posts: 5
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6/21/2006 1:06 PM  
Kai,

There is a [Package] at the beginning with R_pkg, L_pkg, and C_pkg
followed by a pin list with R_pin, L_pin, and C_pin.
Donald Telian
Posts: 42
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7/12/2006 12:05 PM  
Hi Dean,

It's true that the signal at the die is "important" and "what is actually seen by the device".  However, if the memory vendor has written their overshoot spec for the "package pin" then they have accounted for what the die will actually see.  It's common to spec things at points visible to the outside world.  You're using the simulator to "peak" at what is actually going on inside, but most people (particularly those with oscilloscopes!) can not see the waveshape there.  Consequently, IC vendors write specs for waveshapes at the pins.  They know what an overshoot at the pin can cause at the die and have derated their specs accordingly. 

I'd say go with what/where each part vendor has spec'd. 

Donald
Donald Telian
SI Consultant
telian@sti.net
559-760-5793
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Forums > Silicon-package-board > Signal Integrity and Modeling > Should I worry about die signal overshoot?


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