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Subject: Double-counting issue of IBIS model
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sogohsu
Posts: 0
Online: User is Offline
7/03/2005 11:24 PM  
Hi,

As I know, PCB SI is able to process double-couting issue of IBIS model. But, how about Dual-Core case and/or Dual-Processor? In case of complex test load, is it able to define the arbitrary test load by user? Thank you in advance.

BRs,

Sogo Hsu, Ph. D.
Foxconn

lwang
Posts: 0
Online: User is Offline
8/01/2005 9:35 AM  
Hi, Sogo,
Just saw your question.

1. about dual-core or daul-processor question, I think it will depends on what you have. If it fits IBIS's methodologies, PCB SI should be able to handle it;
2. About complex test-loads, for now, DML(Cadence's device model) can have self-define test-loads for differential pairs. In the near future, DML will be able to use self-define single-end test-load as well.

Hope this helps,

Lance Wang
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Forums > Silicon-package-board > Signal Integrity and Modeling > Double-counting issue of IBIS model


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