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Subject: why the same length?
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chenli
Posts: 9
Online: User is Offline
1/05/2007 6:53 AM  
Hi all,

I selected the SDRAM interface signal quality parameter with Kai’s help. But a new problem comes out. I have to determine the trace length limitation of the interface through timing analysis. I wonder whether my understanding is right.

 

If the longest trace satisfies the timing analysis, there is no need to keep the data bus traces the same length. But it is said that the traces of the data bus should be equal length and the address bus also. Why? It confused me a long time.

 

Are there any other limitations, such as data bus vs. DQM…?

Would you please give me some suggestion?

 

Thanks in advance.
Kalevi2
Moderator
Posts: 69
Online: User is Offline
1/05/2007 7:51 AM  
You are asking a question that requires a lot to answer. Please study the application notes for your SDRAM and the memory controller and perform a 0 delay static timing analysis. You have to understand how the memory controller and memory read and write in terms of the control nets, clocks, address, etc. Once you have set up the timing equations, you can simulate with your Manhattan placement to calculate your margins. This will allow you to calculate the required matching.

As an example for a particular DDR2 controller using 1 DIMM, strobes are matched to clock with +/- 400mil tolerance. Each byte lane of data bits and mask is matched to the respective strobe with +/-100 mils. Address and control are matched to clock with +/-500 mils tolerance.

Micron has many good application notes and Freescale has many application notes with their CPU manuals but you are best off with the app notes for the parts you are working with.
Kai Keskinen
drew3rdof3
Posts: 18
Online: User is Offline
1/05/2007 10:39 AM  
Chenli,

As Kai mentioned there are many things to consider which are answered by the app notes and a basic understanding of electronic theory. *All* of the related signals must be there for setup and hold times on the required clock edge which is the reason for length matching and restrictions. In short, timing is everything.

Good luck.
imsong
Posts: 18
Online: User is Offline
2/14/2007 5:59 PM  
Chenli,

Common clock system is not same with Source Synchoronouse Clock System.
Generally, there are minimum and maximum length constraint at Common clock system but in Source Synch. Clcok System,
there are trace length difference constraint for right operation between strobe and data signals.
Find the application note at Micron or google.

Good luck,
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