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Forums > Silicon-package-board > Signal Integrity and Modeling

Subject: Hspice in PCB SI- unable to simulate with MS and vias
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Saad
Posts: 39
Online: User is Offline
2/07/2007 5:49 AM  

Hi,
I am attempting to do Hspice simulations in PCBSi.
I extracted the routed topology from Constraint Manager into SigXp and then replaced the tlsim models by hspice macro models.
So my circuit is driven by cds stimdrvr, microstrip lines, vias and a few hspice input buffer models.
When I run simulation it runs and generate the *lis file with warnings. Section of stdout is attached.
However, if I transform the topology for Constraint manager, all my microstrips are changed to TL and vias are replaced by t-points. This time simulation runs successfully and I see the waveforms in sigwave.

Q1. What does these warning means and how can i eliminate them?
Q2. After transforming the topology how can I be sure that my circuit is intact and includes all RLC parameter of routed traces and vias?

many thanks,
Saad.

*********************** stdout file contents below**********************
Warnings and errors found in listing:

area= 1.00 pj= 0. ikr= 0. amp
expli= 0. amps explir= 0. amps jtun= 0. amps
jtunsw= 0. amps ntun= 30.00

**warning** 23:rll2a0w1000_l8a225w1250defined in subckt via_pc3-6400_rdi resistance limited to 1.000E-05
.
.
**warning** 35:rll14an180w1250_l14a45w1250defined in subckt via_pc3-6400_rdi resistance limited to 1.000E-05

**warning** 35:rll14an180w1250_l20an270w1000defined in subckt via_pc3-6400_rdi resistance limited to 1.000E-05

**warning** 35:rll14a45w1250_l20an270w1000defined in subckt via_pc3-6400_rdi resistance limited to 1.000E-05

HSPICE job main_gen.spc completed.
Wed Feb 7 14:24:41 MET 2007
lwang
Posts: 0
Online: User is Offline
2/07/2007 6:27 AM  
It seems to be due to the minimum resistor value in HSpice. PCB SI field solver may give lower values. This should not effect your simulation results much.
imsong
Posts: 18
Online: User is Offline
2/14/2007 5:53 PM  
Q2 : You should choose right option to exact extraction to SigXP.
You can't miss if you find the option in CMGR to extract, Options => Electrical CSet Extraction => Choose All @ CMGR

Good Luck.
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Forums > Silicon-package-board > Signal Integrity and Modeling > Hspice in PCB SI- unable to simulate with MS and vias


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