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MSkogmo
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5/14/2007 4:15 PM
Hey all. I am trying to create models for two different circuit components. The first is a single pin test node. Basically the schematic symbol has one and only one pin. I need to create a espice or ibis model of this and have been having a really tough time. All I really want this to be is a small capacitiance to ground. This seems to be quite elusive. The second model I am trying to create is for a rnet. The schematic symbol has three sections. Two sections of bussed resistors and one section of power pins. For some reason when I try to apply a si model to any one section I cant "hook it up" to the other sections or to VCC. Some help here?? Matt Skogmo

Donald Telian
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5/15/2007 8:08 AM
Hi Matt, Some times it's the little custom things that are the hardest. We likely need you to clarify a couple things before we're able to answer. 1) Are you working in SigXp or PCB_SI? I'm guessing PCB_SI? 2) The second question is not clear. Maybe we need a diagram? ...or at least more description. Donald

Donald Telian SI Consultant telian@sti.net 559-760-5793

MSkogmo
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5/15/2007 9:02 AM
Donald, We use both SigXp and PCB_SI. At this point, we are extracting the net topology off of the schematic through constraint manager. When we try to extract any net that has one of these test nodes, SigXp complains that all discrete components need models and bails out. I am including a little .gif of the resistor nets. In this particular shot, the three components are labeled RN1,2,3 but in reality, they would all be part of the same network... Notice the pin numbers.

Kalevi2
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5/15/2007 9:03 AM
Matt: If you need to model the test point, you can create an IBIS model using the CDSDefaultProbe and add a package capacitance that corresponds to the capacitance of the pad which you can calculate from the parallel plate capacitance formula using the Area, Dk, and distance to the adjacent plane. Use some small value for R and L. This works OK but slows down your simulations if you are running long lists of nets as the tool will now be trying to measure the signal at the test points and since the default probe has no thresholds, you will get NAs for most of the parameters in the reports. If you can determine the test point is negligible, it is better to change the test points to type IO from type IC (which they usually are) and then they will appear as a connector and not be used in the simulation. I think you are asking how to create an espice model of a resistor pack that has common pins. The sourcelink doc describes this but here is a sample for a 10 pin with pins 5 and 10 common. ("RN_51Ohm" ("ESpice" ".subckt RN_51Ohm 5 1 2 3 4 6 7 8 9 10 R1 1 5 51 R2 2 5 51 R3 3 5 51 R4 4 5 51 R5 6 5 51 R6 7 5 51 R7 8 5 51 R8 9 5 51 .ends RN_51Ohm ") ("PinConnections" ("1" "5" "10") ("2" "5" "10") ("3" "5" "10") ("4" "5" "10") ("6" "5" "10") ("7" "5" "10") ("8" "5" "10") ("9" "5" "10") ) )

Kai Keskinen

Kalevi2
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5/15/2007 9:08 AM
Why would you create two logical parts from 1 physical part? Why not call RN1 the whole 10 pin resistor network. Your BOM will be very interesting and you will have 2 logical symbols for 1 physical symbol.

Kai Keskinen

MSkogmo
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5/15/2007 11:26 AM
Perhaps I chose a poor picture. The way the library part is designed, there are three sections, one section for the "common pins" one section each for the resistor nets. I understand how to make an espice device if the part is all together on one symbol... just like your previous post showed. However if I were to try to stick that espice part onto one of my resistor nets, the pins would not match up because the symbol is logically different than the espice model. Another picture included to try to clarify... Note all are RN1

lwang
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5/17/2007 11:15 PM
Hi, Matt, Per your last explanation, you will have to model RN1 all 10 pins in one discrete part in order to be extracted into Sigxp successfully. Here is the espice part for it: .subckt RN1 1 2 3 4 5 6 7 8 9 10 x5_10 5 10 2pins x1_2_3_4 1 2 3 4 4pin x6_7_8_9 6 7 8 9 4pin .subckt 2pin 1 2 r5_10 5 10 4.7k .ends 2pin .subckt 4pin 1 2 3 4 ra 1 99 4.7k rb 2 99 4.7k rc 3 99 4.7k rd 4 99 4.7k .ends 4pin .ends RN1 I assume the common node for 4pin is not connected to GND. Otherwise, you need to change node 99 to 0 also, you might want to make sure DML Pin Connection lists correct connection combinations. This will beef up the extraction performance as well. Hope this helps, Lance Wang IO Methodology Inc.

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