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Forums > Silicon-package-board > Signal Integrity and Modeling

Subject: si analysis for bus
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binu_eda
Posts: 3
Online: User is Offline
3/09/2005 8:37 PM  
hi,
i have a situation that 4 DSP processor integrated in the board. how to analyis the bus integrity and what topology to fix and the termination .

regards
binu g
horner
Posts: 0
Online: User is Offline
3/10/2005 9:46 PM  
Binu,
This is a pretty open ended question. Basically you need to get the model for the DSP, associate that model to the device on the board, then extract the net into SigXP where you can do a lot of "what if" simulations to help determine the proper termination schemes, topology structures like star, daisychain, ...

All of this is covered in the training course available for Allegro PCB SI.

There are also some pretty good material available on this forum in the form of movies that will help describe this as well. Refer to the movies
Drawing Simulations at the Board Level
and webinar
Archived Webinar: Signal Integrity at the Electrical Engineer Level
both of which can be found in the Movies and Webinars section.
Regards,
John Horner
binu_eda
Posts: 3
Online: User is Offline
3/10/2005 11:47 PM  
i get an error message

"Electrical CSet "Link0" is invalid because :
multiple parts are on the same node. all parts must be connected with T-lines
Using SingXplorer to resolve."

this is the error message i get, when i created a Electrical CSet with name "Link0" and tried to include the differential pair in this Electrical CSet.

how i can resolve this.

regards
binu g
horner
Posts: 0
Online: User is Offline
5/11/2005 12:18 PM  
Binu,
The message you have received is because the topology requires that active devices be connected with the tline object, and not directly connected together with the yellow connection lines. Look in the interconnect tab and add a Tline (or coupled tline for your diffpair) between the IC's.
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