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Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include: - Ability to respond to posts via e-mail
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Visit the new Cadence Community today at www.cadence.com/community and join the discussions! Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy. Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.Best regards, Mike and Tom Michael A. Catrambone - Steering Committee Chairman Distinguished Engineer PCB/Mechanical UTStarcom, Inc. Tom Diederich Cadence Community Manager
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buenos
Posts: 14
Online: 
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| 1/05/2008 6:35 AM |
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hi.
who does SI/PI simulations: hw engineer or layout designer? if there is no SI engineer.
do all companies use the allegro simulation capabilities? (at least reflection analysis)
and anyway, how much control does the hardware engineer have over the layout:
can he say to the layout engineer this?-"put these 10 capacitors here and not there" or "put the termination here" or "make this splitplane wider"...
who specifies the layer stackup, materials, trace widths, footprint assigments, bus-layer assigments... |
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Kalevi2
Moderator
Posts: 69
Online:
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| 1/07/2008 3:53 AM |
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In general, the PCB layout person does not have the background to be able to do the SI/PI simulations. Some companies or departments simulate, some don't. More of them should. The H/W engineer has significant control over placement but it is a balance between mechanical, thermal, ease of routing, I/O locations, etc. It is usually a team effort. The first placement is sometimes done using post-IT notes on a piece of cardboard. Location of terminations is driven by signal integrity considerations.
Stackup, trace widths, and dielectric material are a balance between cost, impedance requirements, routing difficulty, emi/noise requirements, how many DC voltage planes are needed, etc.
It sounds like you are new to the hardware design process. Spend some time talking to an experienced hardware designer. |
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Kai Keskinen
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buenos
Posts: 14
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| 1/07/2008 5:41 AM |
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thanx the answer.
i am not new to hardware development, but I was working in an unusual way until now, but I want to change to another company. Most of them work in the usual way, which is new for me. Until now, I was doing everything, and its not clear for me, what tasks will remain for me, and what will not. |
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buenos
Posts: 14
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| 1/14/2008 1:58 AM |
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and who does the schematics-level design and assigning footprints to schematics-symbols?
(I hope not the layout designer, but the HW design engineer.)
everywhere? |
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Kalevi2
Moderator
Posts: 69
Online:
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| 1/14/2008 4:11 AM |
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| The design engineer is supposed to do the schematic level design and a CAD librarian does the footprints. If you are a small outfit, the layout guy probably is the librarian and does the footprints. |
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Kai Keskinen
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buenos
Posts: 14
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| 1/14/2008 6:43 AM |
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| thanx again. |
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buenos
Posts: 14
Online:
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| 2/17/2008 8:40 AM |
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the librarian or layout guy does the schematic part symbol creation as well? or they do only the footprints, but not the schema symbols? (in case if there is no librarian, only hw and layout engineers. i am going to work at a company like this, from next month)
so, who has the Allegro PCB Librarian software license? bot the HW and the layout eng, or only the layout person?
If the layout guy makes even the schematic symbols (with property assigments, like package choice, vendor name, value, tolerance...) then how can it work? As a HW design engineer, I will have to ask him 10x a day, to "please create a part for me"?
These lots of parameters are very important, and i think only the HW engineer knows them correctly. Maybe I need 1 new footprint every second day, but I need new sch symbols 10x a day, with assigning standard footprints from an existing library. |
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Kalevi2
Moderator
Posts: 69
Online:
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| 2/19/2008 4:30 AM |
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| Some companies have the hardware designer do the schematic symbol and a librarian do the physical symbol. Some companies, especially the larger ones, have the hardware engineer request the component engineering group to do both of these things. It appears you are at a smaller company where you as the HW engineer will probably have to do a lot of what would be done by a component engineering group . Having your licenses on a WAN would solve who has what license. If you are at a new company just starting up, your management should be planning on how this is going to be organized. Most established companies have a standard way of doing the schematic symbols. You might want to start this thread on the PCB Design group. |
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Kai Keskinen
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