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Subject:  RTL compiler: Port names expansion of record types in vhdl synthesis
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sulabhv
Posts: 1
Online: User is Offline
6/13/2006 11:23 PM  
I am synthesizing a vhdl netlist with pacakge declarations .The verilog o/p netlist has PORT names  expanded with record elelents .
Is there a method where port names are output in the verilog as it is "without" the record elements.
eg:
type A is record
x:std_logic_vector(15 downto 4);  
end record;

o/p of verilog netlist is  "port_name[x] " ;in ⎛:0]

what should be dont to get only  ---> port_name 
I have already tried the following variables;
hdl_record_naming_style
change_names

Thanks
sulabh

evenditti
Moderator
Posts: 23
Online: User is Offline
8/21/2006 8:53 PM  
I may ask a stupid question but why are you using a record, especially in the example you are providing? If you want to synthesize you RTL you need to use only bit (std_logic) and vectors (std_logic_vector), no enumerated types or anything else as it can not be properly represented after synthesis.

So my recommendation is that you modify your VHDL so that your interface is not using record and then everything should be well.

Eric.
Eric Venditti
bryan
Posts: 25
Online: User is Offline
11/27/2006 6:24 AM  
Narrow minded advice. Records and Stucts in SV are extremely useful to the RTL designer. They create groups of signals which are easy to manage as you move up and down the hiearchy. Very easy to add a port to 10 levels of hierarchy when using records.

A good synthesis tool would allow for a "bit", as is, and expanded representations. "Bit" would be the entire record as one long bit string. As is implies using the Record definition. Expanded is the Signal with some reasonable exanded definition using the record element names.

I've been using Records in VHDL in another vendor's Tool since the mind 90's.
Regards,
Bryan
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Forums > Digital IC > Synthesis and test > RTL compiler: Port names expansion of record types in vhdl synthesis


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