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PNR
Posts: 4
Online: 
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| 8/25/2006 5:49 AM |
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Hi Everybody,
I have a problem with a sdf-annotated netlist during elaboration before simulating it with ncsim.
I get the following output for severall cells during elaboration:
input C,D,SN;
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ncelab: *W,SDFNMX (/home/xxxxx/CORELIB_sdf3.0.v,1981|6): SDF annotation on segment 'tb_registerbank.registerbank_i.dataout_control_i.\rd_cnt_regΏ] .C' will be ignored.
Here is the corresponding part in the Verilog-Simulation-File:
module Flip-Flop (C,D,Q,QN,SN);
output Q,QN;
input C,D,SN; //line 1981
`ifdef functional
U_FD_P_SB_NO (buf_Q,D,C,SN,1'b1);
`else
reg notifier;
U_FD_P_SB_NO (buf_Q,D,C,SN,notifier);
`endif
buf (Q,buf_Q);
not (QN,buf_Q);
`ifdef functional
`else
specify
(posedge C => (Q:D)) = (1,1);
(posedge C => (QN:D)) = (1,1);
(SN => Q) = (1,1);
(SN => QN) = (1,1);
$setup(posedge D, posedge C, 0, notifier);
$setup(negedge D, posedge C, 0, notifier);
$recovery(posedge SN, posedge C, 0, notifier);
$hold(posedge C, negedge D, 0, notifier);
$hold(posedge C, posedge D, 0, notifier);
$removal(posedge SN, posedge C, 0, notifier);
// $hold(posedge C, posedge SN, 0, notifier);
$width(posedge C, 1, 0, notifier);
$width(negedge C, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
`endcelldefine
I have changed this cell (and the other ones, that throw that warning), to make it sdf3.0-compliant. Ncelab finds all timing-arcs within the cell (at least it prints no errors, that it doesn't find one). I have to admit, I am not quite sure which timing-arc ncelab is ignoring.
Could anyone please tell me, where the error lies in the Verilog-Simulation-File (if any) or where to find an explanation for the ncelab error codes (see title)?
Another Problem with ncelab, that I am having, is that it is also ignoring INTERCONNECT timing arcs, which are 'interfacing' with a macrocell, that was going to be simulated as a transistor-netlist (no verilog-simulation-file does exist).
I'd appreciate any help, thank you.
Bye, PNR
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ajeetha
Posts: 0
Online:
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| 8/29/2006 10:13 AM |
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Hi,
Not sure if I understood your problem well enough, but try:
nchelp ncelab
HTH
Ajeetha, CVC
www.noveldv.com
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EngHan
Posts: 65
Online:
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| 8/31/2006 8:53 PM |
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Hi PNR,
Will need to look at the lines in SDF that is giving the warning (is it line 1981?). Look at the SDF, and then the lines between "spcify"/"endspecify" in the verilog model, you may figure out the issue. Possible causes are:
1. separate setup and hold, or just setuphold syntax used.
2. leading posedge/negedge in verilog model but not in .lib (which is used by the tool to generate the SDF).
3. separate recovery/removal vs. recrem
4. ??etc??
Regards,
Eng Han |
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PNR
Posts: 4
Online:
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| 9/01/2006 7:44 AM |
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Hi,
thanks to ajeetha. The information given by nchelp for mnemonic SDFNMX:
[quote]
ncelab/SDFNMX =
SDF annotation is not permitted on any segment (both digital & analog) of mixed-signal.
The annotated delay will be ignored, and circuit will be simulated without delay.
[/quote]
This explains the second problem, I was having. Every INTERCONNECT timing arc, that is interfacing with the makro (to be synthesized as a verilog-ams-netlist), throws that warning. The ignorance of the analog nets is ok, their delays are negligible small anyway. But I would really like ncsim to respect the sdf-annotation on some digital nets. The problem goes that far, that all INTERCONNECTS on the pathes from the input-pins to the makro are ignored.
But I did not find a way to declare a net as digital in a transistor-level-verilogams-netlist nor to tell ncelab to strictly honor these interconnects. I don't suppose, there is a way?
(If I declare the signal digital in the testbench, ncism will not run, because it doesn't know how to interpret this signal at the makro.)
@EngHan:
The lines given by the warning-message are the ones in the verilog-simulation-file. So, I can't be sure, which ones in the SDF are ignored. But since I changed the simulation files for sdf3.0-compliance because of sdf-warnings, that the timing arcs to be annotated cannot be found (in some sequential cells), I think, these warnings refer to INTERCONNECT arcs.
...
Oh, guys, I am sorry for the fuss, I just found out, what caused the warnings with the sequential cells: I still had the generated clock in the testbench (from an earlier version of the block under test), described as an analog signal. That's all.
That only leaves me with the real mixed-signal problem. *g*
Thanks for your help.
Bye, PNR. |
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