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Forums > Digital IC > Synthesis and test

Subject: using RTL Compiler as Static Timing Analysis
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sporadic crash
Posts: 43
Online: User is Offline
11/29/2006 2:34 PM  
I set up the libraries, read the netlist, read the SDC. Now I want to access the paths which are unconstrained. But I cannot find a corresponding command. Is it possible to generate the list of unconstrained paths using "report timing" command?
Stalker
Posts: 24
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11/30/2006 1:36 AM  
Hi,
The command "report timing -lint -verbose" will give you all unconstrained input and outputs.
Maxim R.
sporadic crash
Posts: 43
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12/11/2006 12:17 PM  
Thank you very much for the kind info.
sporadic crash
Posts: 43
Online: User is Offline
1/04/2007 12:03 PM  
Additional question regarding this issue:

Maybe it will be ridiculuous to ask, but does setting cost groups/path groups in the flow stated in the first posting of this thread (ie. setup lib, read netlist, read SDC, gen reports) have effect on the timing results?

Does the timing analyzer engine in RC take cost/path groups into account?
sporadic crash
Posts: 43
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1/06/2007 9:36 AM  
I put my question other words:

when I use RC as an STA Tool, does the change of cost/path groups in a design have an effect on timing analysis calculations? For ex:
1. setup lib, read netlist, read SDC
2. define a cost/path group setting
3. report_timing
4. change cost/path groups
5. report_timing

Can the timing analyzer inside RC called by report_timing generate different results? Does any change on cost/path groups change the behavior of analysis?

Please note that I DON'T USE RC for synthesis but for [b]static timing analysis[/b].
grasshopper
Posts: 48
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1/19/2007 7:48 AM  
Greetings Sporadic Crash, as far as I know, cost groups should have no effect on delay calculation. Cost groups serve two main purposes in my mind: + guide the optimization engine when a slow memory or part of the logic is affecting the targets for the whole design + for reporting purposes if you need to categorize based on some criteria good luck, G-
evenditti
Moderator
Posts: 23
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1/23/2007 10:59 AM  
One of the thing that happen when you create path groups is that a path that used to be reported in a default group is not anymore so the path orders might be different but if you do a report_timing point to point it should still be the same before and after just the group might be different.
Eric Venditti
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Forums > Digital IC > Synthesis and test > using RTL Compiler as Static Timing Analysis


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