Thursday, November 20, 2008     Register | Login | Search | Contact Us
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Subject: Clock gating cells constraints
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
Stalker
Posts: 24
Online: User is Offline
12/04/2006 9:06 AM  
Hello,

    I have multicycle paths from control registers to enable pin of clock gating cells.
In RTL - Compiler CG cells are added only during synth -to_map stage, after synth -to_gen there are no "unmapped" CG cells. This forces me to add multicycle paths to CG cells only after mapping.
It causes significally increased runtime, because during the mapping RC tries to close path to the enable of CG cell and work less on other pathes. The CG constraints are set after the mapping and incremental synthesis is used to close other paths, that still remain violated.
    Any suggestion how to set the constraints before mapping?

Thanks in advance.

Maxim R.
Posting to forums is available to community members only.
Login or Register

Forums > Digital IC > Synthesis and test > Clock gating cells constraints


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.