sporadic crash
Posts: 43
Online: 
 |
| 12/11/2006 11:31 AM |
|
I have a clock named "clk_design". How can I constrain all paths between input ports and this clock?
I have applied following:
define_cost_group input_to_clk_design
path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path
But when I apply report timing -cost_group input_to_clk_design, report tells me that no path group has been found.
Any ideas? What shall i give as -to option for path_group?
|
|
|
|
synthman
Posts: 17
Online:
|
| 12/11/2006 11:48 AM |
|
| Clock object is a valid object of the -to option. Look at the 'exceptions' attribute of the cost group to see if any path group exist. If the path_group does exist, look at the 'paths' attribute of the path_group to see if there is any path. |
|
|
|
evenditti
Moderator
Posts: 23
Online:
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:10 PM |
|
I see following:
- cost_group input_to_clk_design exists
[b]rc:/> ls -attribute /designs/*/cost_groups/input_to_clk_design[/b]
/designs//timing/cost_groups/input_to_clk_design (cost_group)
Attributes:
exceptions = /designs//timing/exceptions/path_groups/input_to_clk_design_path
[b]rc:/> ls -attribute /designs/*/exceptions/path_groups/input_to_clk_design_path[/b]
/designs//timing/exceptions/path_groups/input_to_clk_design_path (exception)
Attributes:
cost_group = /designs//timing/cost_groups/input_to_clk_design
domain =
exception_type = path_group
from_points = /designs//ports_in/...
paths = specify_paths -from {/designs//ports_in* ...
priority = 90
to_points = /designs//timing/clock_domains/domain_1/clk_design
rc:/>
Now report timing -cost_group input_2_clk_design
Shall I define the clock with "domain"? |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:12 PM |
|
The last sentence in the previous posting is incomplete:
[b]report timing -cost_group input_to_clk_design[/b]
gives me
no paths found.
|
|
|
|
evenditti
Moderator
Posts: 23
Online:
|
| 12/11/2006 12:17 PM |
|
if you pick one of the input port and do report timing -from input_port_name, what do you get?
|
|
Eric Venditti |
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:24 PM |
|
report timing -from /designs//ports_in/
Exception : 'path_disables/_line_2563'
Timing slack : UNCONSTRAINED
Start-point :
End-point :
(u) : Net has unmapped pin(s).
It seems it is still unconstrained.
I have used following commands:
1. create_clock -period $period -waveform [ list $rise $fall ] [ get_ports {clk_design} ] -domain clk_design
2. define_cost_group -name input_to_clk_design
3. path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path
report timing -cost_group input_to_clk_design
tells me no path found.
|
|
|
|
synthman
Posts: 17
Online:
|
| 12/11/2006 12:30 PM |
|
What version of RC do you use? Do you have any path from input ports that goes to registers clocked by clock clk_design? Try this command to see where the input port fanouts to:
fanout -end |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:34 PM |
|
yes definitely I have. I have implemented this design :)
fanout -end
gives me a long list!
What am I missing here??? It must be simple..
1. create_clock
2. define_cost_group
3. path_group
What else? What am I doing wrong?
RC is 6.1.
|
|
|
|
synthman
Posts: 17
Online:
|
| 12/11/2006 12:38 PM |
|
You need to define input delay with external_delay command. If you don't have that, report timing will show the path as unconstrained, but it would show the path from input to register.
Try to report timing from register to register, if it shows no path, then it might be something wrong with the library. |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:46 PM |
|
external_delay helped.
I did not do it. Instead, I applied "dc::set_input_delay" to an external pin.
It is not enough, it seems so. What you think?
|
|
|
|
synthman
Posts: 17
Online:
|
| 12/11/2006 12:51 PM |
|
| dc::set_input_delay should work, how do you apply it? |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 12:54 PM |
|
set_input_delay $delay -clock clk_designl $inputs
it is called from an SDC file. I have written in the previous posting to imply that I have used an SDC style, not RC style.
Am I missing anything here?
|
|
|
|
evenditti
Moderator
Posts: 23
Online:
|
| 12/11/2006 12:59 PM |
|
In your previous email you wrote
1. create_clock
2. define_cost_group
3. path_group
You need to read the sdc between 1 and 2. not before 1 or after 3.
Eric. |
|
Eric Venditti |
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 1:02 PM |
|
1. create_clock is in an SDC file, called by another TCL script, using "read_sdc".
2. and 3. are in the TCL script, after the read_sdc call.
after external_delay, I have applied dc::set_input_delay again, RC tells me that external_delay is removed.
Are both commands equivalent, ie. "dc::set_input_delay" and "external_delay"?
|
|
|
|
synthman
Posts: 17
Online:
|
| 12/11/2006 1:10 PM |
|
| external_delay is equivalent to both dc::set_input_delay and dc::set_output_delay. Your command sequence looks correct, not sure what the problem is without seeing all the data. If you have access to Cadence Support, send in the data. |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/11/2006 3:17 PM |
|
|
Hi Eric,
I have read all the postings and have read your last sentence in one of your previous postings again:
"...for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group."
That means RC covers this path. I am not at my desk now, but will check it as soon as possible. Then that means when I define cost_group for a clock domain, then I do not need to define -from "external_port" to a clock domain.
I am using this tool for my first time, but it is pretty similar to Xilinx constraint mechanism. However RC is more "intelligent" about assigning clock domains.
I will return you when I get news things. |
|
|
|
Stalker
Posts: 24
Online:
|
| 12/12/2006 4:39 AM |
|
Hi,
You can try the following:
include load_etc.tcl
define_cost_group -name I2C -design $DESIGN
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
foreach cg [find / -cost_group *] {
report timing -cost_group $cg >> $RPT_NAME
}
It creates path group from all inputs to registers, sampling the data from the inputs.
The clock and input delays should be defined before. |
|
Maxim R. |
|
sporadic crash
Posts: 43
Online:
|
| 12/12/2006 4:45 AM |
|
I think
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
is an overkill in a multi-milliongate design, because RTL Compiler by default definition will try to analye "all flipflops" in the design, which costs a lot of runtime.
IMHO, the clock domains must be grouped separately. |
|
|
|
sporadic crash
Posts: 43
Online:
|
| 12/12/2006 7:50 AM |
|
Hi,
I have found the reason, why I don't see that any path found for the port I have selected.
It has to do with that I have unknowingly set a "default" input delay just before the corresponding set_input_delay, which takes the port to another clock domain.
Therefore the second dc::set_input_delay does not take the port to another clock domain, unless the previous is removed. Therefore RTL Compiler does not find a path between the port and the clock domain I wanted, unless there is no "dc::set_input_delay" defined for the clock domain.
Thanks folks. your messages helped me a lot. Especially Eric's email. |
|
|
|