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Subject: Clock networks in RC
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adi_j
Posts: 4
Online: User is Offline
12/29/2006 10:45 AM  
Hi.
This question is related to myazdani's question.
I'm looking for the equivalent command of DC's "set_ideal_network" especially in connection to clock networks - as far as considering the literature, I've understood clock networks are automatically treated as ideal so I have few questions I'd be happy to get an answer on:
1. Is what I wrote correct - are clock networks automatically treated by RC as ideal?
2. How can I manually set and unset this property on any net I desire? I haven't been able to find the answer in the manual.

Thank You,
Adi.
galaxy_jason
Posts: 2
Online: User is Offline
1/17/2007 3:48 PM  

1) Yes, clock networks are ideal by default.

2) I think you want to set the ideal_network attribute, or do set it with SDC. See the RTL Compiler
Attribute Reference Manual

ideal_network
ideal_network {true | false}
Default: false
Read-write attribute. Sets the network of the specified driver pin to an ideal network. The pin
must be a driving pin. This attribute propagates through combinational gates, latches, and
hierarchical boundaries, unlike the ideal_driver attribute.....etc.
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Forums > Digital IC > Synthesis and test > Clock networks in RC


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