Tuesday, January 06, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Synthesis and test

Subject: Passing Defines during read_hdl
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
bryan
Posts: 25
Online: User is Offline
4/16/2007 7:34 AM  
I'm looking to see how to pass defines during the read_hdl RC command.  Below is an example.  I've tried many variations but just can't seem to get it working.

read_hdl -sv -define {tpd} -top genmemory_mp {../../common/rtl/csco_routines.v   ../rtl/genmemory_mp.v}
Regards,
Bryan
grasshopper
Posts: 48
Online: User is Offline
4/16/2007 8:40 PM  
Hi Bryan,

tried something similar and it worked as expected. I wonder if it is something in the RTL or maybe try without the -top option. I did a man on read_hdl and it seems to indicate that -top is related with structural netlists. Since you have an `ifdef I am assuming it is not structural although not necessarily the case. I usually read_hdl everything and specify the top on the elaborate command but RC seems to do a pretty good job figuring it out by itself anyhow. Here is my short example if you find it useful:


module define_hdl (
input wire in, clk,
output wire out
);

reg pipe0;

`ifdef use_neg_edge
always @(negedge clk) begin
pipe0 <= in;
end // always @ (negedge clk)
`else
always @(posedge clk) begin
pipe0 <= in;
end // always @ (posedge clk)
`endif

assign out = pipe0;

endmodule // define_hdl

good luck,
gh-
bryan
Posts: 25
Online: User is Offline
4/17/2007 12:23 AM  
Well, I tried the exact same command today and it works. Not sure what was going on but none the less, problem resolved.
Regards,
Bryan
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Synthesis and test > Passing Defines during read_hdl


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.