Wednesday, February 08, 2012     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Synthesis and test

Subject: How to convert netlist 2 lib file
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
mattan
Posts: 0
Online: User is Offline
5/05/2007 11:08 PM  
Hi How can I convert a nelist to a lib file with timing constrain ? Thanks
grasshopper
Posts: 48
Online: User is Offline
5/06/2007 8:28 AM  
Hi Mattan,

I believe FE / SOC have a command called do_extract_model that will analyze all of the paths and create a .lib based on timing and setup/hold constraints for the I/Os. I personally have not tried it but it sounds like it may do what you need. I would be curious to hear how it goes since I may need it in the future.I suspect Primetime or ETS can do this as well.

good luck,
gh-
mattan
Posts: 0
Online: User is Offline
5/06/2007 9:52 PM  
Hi

Thanks , what do you mean by FE/SOC which license this tool require ?

Mattan
hiram79
Posts: 1
Online: User is Offline
5/24/2007 12:25 AM  
do_extract_model works with SOC5.2 and above. It just uses encounter license. The important task would be to do a QA on the extracted .lib. For that your constraints file should be proper. The .lib extracted using the above method contains only Input to output paths. Basically its a black-box. So, you might need to spend a lot of time tweaking the constraints.
zhjjg
Posts: 2
Online: User is Offline
4/21/2008 6:59 PM  
Would you please tell me how to decide the input transition time range and output load range???

Thanks a lot.
grasshopper
Posts: 48
Online: User is Offline
4/22/2008 5:49 AM  
Hi zhjjg,

input transition time is frequently a percentage of your clock period and your library team or vendor can provide you with a good guidelines for this. Similarly for output load range.

gh-
zhjjg
Posts: 2
Online: User is Offline
4/22/2008 9:53 PM  
Thanks!!

Currently I try to generate the lib file for a Mixed signal IP design.
According to your reply, Is it that I can get the input transition time and output load for a pin based on the related clock period?
grasshopper
Posts: 48
Online: User is Offline
4/24/2008 9:01 AM  
To some extent. Obviously not all libraries are create equal but in the absence of any guidance, you should be able to derive these number from your clock speed targets. You certainly need to make sure that your clock speed targets are reasonable for the technology you are using, otherwise you will be spending some sweet time in timing closure.

regards,
gh-
arunrach
Posts: 17
Online: User is Offline
7/02/2008 1:52 PM  
Hi,

Im am trying to use do_extract_model to create a .lib file. I am using this in the top level of another netlist in  build gates. However I see that, when I run the flat netlist (no .lib used for sub block) I see some timing violations which I dont see on using the .lib file.

When I study the timing report, I see that the sub block (with .lib) shows a different propagation delay which is much lesser than what it actually is. Can you please let me know the reason for this? And when extracting the .lib file how are purely combinational paths handled?

Thanks,
Arun
arunrach
Posts: 17
Online: User is Offline
7/02/2008 1:52 PM  
Hi,

Im am trying to use do_extract_model to create a .lib file. I am using this in the top level of another netlist in  build gates. However I see that, when I run the flat netlist (no .lib used for sub block) I see some timing violations which I dont see on using the .lib file.

When I study the timing report, I see that the sub block (with .lib) shows a different propagation delay which is much lesser than what it actually is. Can you please let me know the reason for this? And when extracting the .lib file how are purely combinational paths handled?

Thanks,
Arun
grasshopper
Posts: 48
Online: User is Offline
7/02/2008 2:14 PM  
Hi Arun,

this seems like a question for the support folks @ Cadence. I have used the command but cannot really say that I know that level of detail how the combo paths are characterized. I think the support guys should be able to better help u with that.

gh-
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Synthesis and test > How to convert netlist 2 lib file


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.