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Forums > Digital IC > Synthesis and test

Subject: synthesis System Verilog design
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SHL
Posts: 8
Online: User is Offline
7/05/2007 5:05 AM  
Hi there,

I am a new user in System Verilog and wish to gain some help here.
Do anyone know how to synthesis System Verilog design? Which CAD tool should I use?and how?
grasshopper
Posts: 48
Online: User is Offline
7/05/2007 5:56 AM  
Hi SHL.

RTL Compiler has pretty extensive support of the System Verilog(IEEE 1800) syntheiszable subset. The use is pretty simple as far as I am concerned; simply add the -sv switch when you do read_hdl and that is all I had to do.

gh-
SHL
Posts: 8
Online: User is Offline
7/05/2007 8:15 AM  
hi gh,

Actually i have tried to use Altera Quartus and Synplify Pro to synthesis my SV design. I added the .sv file when read_hdl, but when i start to run, it complain that no HDL files found.
so i was wondering whether the process of synthesis VHDL file is the same as SV file or not.
Do you have any proper user guide to synthesis a SV file? mind to sent me?
thank you
grasshopper
Posts: 48
Online: User is Offline
7/06/2007 6:06 AM  
Hi SHL,

sounds like you never read the RTL to me. In my case it was quite simple:

> read_hdl -sv {file1.v file2.v file3.v }

If you cannot find the file, it has little to do with SV. Check your hdl_search_path and the paths you entered.

good luck,
gh-
SHL
Posts: 8
Online: User is Offline
7/06/2007 6:57 AM  
Hi gh,

I am a little bit confused here. I thought that a system verilog code will have .sv extension after its name? but you just mention
{file1.v file2.v file3.v }.... ?
grasshopper
Posts: 48
Online: User is Offline
7/06/2007 7:30 AM  
SHL,

a file can take any extension you want. Different design teams use different design practices and naming conventions. Some use .v, .v2k., .sv, .vg, .VG, .VRL, .VHD, .vhd, .verilog, .VLOG, .rtl, etc. You catch the drift... The tool does not care about the extension you choose but you do need to tell the tool what HDL language you are using hence the '-sv' switch needed in your read_hdl command.

hope this helps,
gh-
SHL
Posts: 8
Online: User is Offline
7/06/2007 8:52 AM  
hi gh,
Thanks for the help. I think Synplify Pro 8 doesn't recognize .sv file. After i change my file's extention to .v and use the -sv switch, it can synthesis now.
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Forums > Digital IC > Synthesis and test > synthesis System Verilog design


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