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Forums > Digital IC > Synthesis and test

Subject: How to set_current_module in RTL Compiler??
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spveer
Posts: 6
Online: User is Offline
7/07/2007 1:00 PM  
Hi all,

I need to perform synthesis of a sub-block of the design. And then merge it with the top design.
I am using RTL Compiler.

In pks or build gates this was simple, we had the command set_current_module .. and one can then perform synthesis on a subdesign.

There seems to be no direct equivalent of set_current_module in RTL Compiler.

I found one command in RTL Comiler, derive_environment.
This promotes a subdesign to a topdesign.
So in design database we will now have
/designs/topdesign
/designs/subdesign_promoted_top

The synthesis which I perform on /designs/subdesign_promoted_top is now independent of actual topdesign.

This  works. But how can I later merge the
/designs/subdesign_promoted_top
into
/designs/topdesign ??

I see no way to do this in the userguide!

Can someone help me?

Thanks in advance,
Pradeep
Stalker
Posts: 24
Online: User is Offline
7/07/2007 9:27 PM  
Hi Pradeep,

Try the following:

edit_netlist new_instance -name /designs/subdesign_promoted_top /designs/topdesign

There are more options for "edit_netlist new_instance" in the manual

Regards,
Max
Maxim R.
Stalker
Posts: 24
Online: User is Offline
7/07/2007 9:29 PM  
Sorry, tipo:
edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign
Maxim R.
spveer
Posts: 6
Online: User is Offline
7/08/2007 12:06 AM  
Thanks Stalker,

I will try this tomorrow, when I am in office..

But what should I do with the existing subdesign in the topdesign..?
will that be overwritten?

Or should I first remove the existing subdesign, and then create a new instance using the subdesign_promoted_top?

Can you please tell me if possible, about how merging takes place...

Thanks,
Pradeep
Stalker
Posts: 24
Online: User is Offline
7/08/2007 12:23 AM  
You can continue working with you topdesign as usual, the only thing, that you can't omit the design name in the commands, for example:
write_hdl topdesign > top.v
and not
write_hdl > top.v
I don't know exactly how the new instance is linked, but I think the subdesign_promoted_top is needed for correct work.
Maxim R.
spveer
Posts: 6
Online: User is Offline
7/09/2007 1:15 AM  
Hi Max,

I tried using this...
edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign

now on the topdesign I have an unconnected instance in the hierarchy,  called SUBDESIGN_INST_NAME

If I try to optimize, since this instance is unconnected, and not driving any ports, the instance is removed by synthesis.

------
I also tried the following:

The hierarchy looks like this:
/designs/topdesign/instances_hier/xxxx
/designs/topdesign/instances_hier/subdesign  ----- this is promoted to subdesign_promoted_top
/designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign


now I removed subdesign
rm /designs/topdesign/instances_hier/subdesign

So the hierarchy now looks like this:
/designs/topdesign/instances_hier/xxxx
/designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign

then I have run 'synthesize'... But however the tool sees /designs/topdesign/instances_hier/SUBDESIGN_INST_NAME, not driving any ports and optimizes it away.... but doesnt link it to topdesign!! :(

----

I am still not sure, how to link the designs....
grasshopper
Posts: 48
Online: User is Offline
7/09/2007 7:22 AM  
Hi Pradeep,

have you tried the change_link command. I have used this in the past in a similar flow with pretty good success. I think the key is that the pin names have to match.

gh-
spveer
Posts: 6
Online: User is Offline
7/09/2007 8:03 AM  
Hi gh,

yes,  change_link works...!
i was just trying that and got ur mail too :)

thanks n regards,
pradeep
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Forums > Digital IC > Synthesis and test > How to set_current_module in RTL Compiler??


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