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Subject: SDF file and HOLD time and SETUP time
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houmanh
Posts: 21
Online: User is Offline
7/19/2007 10:59 AM  


Hi,
I am just starting using the nano encounter tool. I just wonder if the sdc file we give to the encounter tool should be the same as SDC file we give to the RTL compiler?
I want to connect my synthesized block to a memory with specific setup hold time. Does anyone has an idea how to give the encounter tool the specific setup time and hold time? how to put a constrain on its output and input port for setup and hold time?

Thanks,

Houman
jflieder
Posts: 10
Online: User is Offline
7/19/2007 12:30 PM  
Houman,
It sounds like you are trying to model the external environment around your chip. This would typically be done using the set_input_delay and set_output_delay SDC constraints. Both of these have a -min and -max option that will allow you to accurately model the setup and hold time to/from your memory block. Be advised that RTL-Compiler will not use the -min constraints but will save them and write them out for SOC-Encoounter. The reason for this is that RC does not do any hold time fixing as this is best left until after P&R.

Regards
houmanh
Posts: 21
Online: User is Offline
7/30/2007 2:26 PM  
Hi,

Thanks fo rthe information.
Now my setup time is fine. But I still have problem with hold time.
The problem is that the encounter tool disregard the hodl time I define for specific port in the sdc file using the command below:

set_output_delay -clock [get_clocks {clk}] -min 0.4 [get_ports {mem_d}]

where I want to have a 400ps hold time.

Thanks.

Houman
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Forums > Digital IC > Synthesis and test > SDF file and HOLD time and SETUP time


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