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Subject: Can't simulate with gate delays.
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JoeArny
Posts: 3
Online: User is Offline
8/01/2007 5:53 AM  
Hi, I'm new in hardware designs and cadence tools, and I read allot of texts but I'm still with a doubt:

How can I simulate my design after synthesis with gates delay!?<br><br>I'm doing these comands in RC Compiler to synthesize: <br><br><code>set_attribute library /eda/xfab/xh035/cadence/xh035/D_CELLS.lib<br>read_hdl time_base_timer.v<br>read_hdl edgedetect.v<br>elaborate
define_clock -period 125000 -name fc_clk_i<br>synthesize -to_mapped<br>write_sdf > done_tbt_delay.sdf


After that I'm using nclaunch to simulate, and doesn't matter if I use or not the sdf file every single gate stay with a delay of 100ns.

Anyone know something about it? I didn't find nothing about it in this forum...

Thanks!

PS: I'm using the xfab lib.
grasshopper
Posts: 48
Online: User is Offline
8/01/2007 6:06 AM  
JoeArny,

this, most likely has little to do with RTL Compiler an more to do with your simulation setup. Make sure you have simulation models for the cells and that you have setup all your compiler directives appropriately. `UNIT_DELAY is one commonly used to switch gate delays between a generic number and the one coming from the annotation. Also verify that the SDF got annotated without erroring when you read it in. For additional details on the simulation setup I would post on the simulation forum if there is one.

good luck,
gh-
JoeArny
Posts: 3
Online: User is Offline
8/01/2007 7:33 AM  
Hi grasshopper, thanks about your reply..

I'll read more about the nclaunch and go to simulation forum, as you said. :)

About UNIT_DELAY, thanks about the Tip...!!! ;)

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Forums > Digital IC > Synthesis and test > Can't simulate with gate delays.


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