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Subject: generating SPICE netlist from verilog RTL using RC or nanoencounter
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houmanh
Posts: 21
Online: User is Offline
8/03/2007 12:47 AM  
  Hi,
I was just wondering if it is possible to generate spice netlist from verilog RTL using any of RTL compiler or nanoencounter tool? I have the spice model for standard cell.

Thanks,

Houman

EngHan
Posts: 65
Online: User is Offline
8/03/2007 1:31 AM  
Hi Houman,

I am using Calibre for DRC and LVS. Calibre has a utility to convert verilog to spice.

By the way, you cannot convert Verilog RTL to spice. But you can convert Verilog gate level netlist to spice.

Regards,
Eng Han
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Forums > Digital IC > Synthesis and test > generating SPICE netlist from verilog RTL using RC or nanoencounter


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