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Forums > Digital IC > Synthesis and test

Subject: RC see paths through the memories.
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Stalker
Posts: 24
Online: User is Offline
8/30/2007 12:17 AM  
Hi All,

I see violating paths from ports through memory (D->Q) to the register.
These paths should not appear, because memory is sequential element and all the paths to D pin should stop there, but they don't.
Have anyone saw similiar issue?
Can I just disable timing arcs from D to Q inside the memories?
Thank you in advance,
Maxim R.
clsantos
Posts: 31
Online: User is Offline
8/30/2007 7:55 AM  

It will depend on the lib file of the used memory.
Memory should be described as a sequential cell for input pins be considered as end points.
If you disable timing arcs from D to Q so true paths beginning at memory pins will be affected.

Cristiano.
evenditti
Moderator
Posts: 23
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8/30/2007 7:58 AM  
I have seen that in primetime before. The root cause at the time was that some test pin was controlled incorrectly (missing case analysis or incorrect case analysis) and the memory had a bypass mode feature for DFT. Has Cristiano mentioned looking at the .lib is the best to figure out why you are seeing this.
Eric Venditti
grasshopper
Posts: 48
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8/30/2007 8:04 AM  
Hi Stalker,

this is pretty common and usually due to the AWT or Asynchornous Write Through functionality of memories. Usually it is used for DFT purposes but one could use it for anything else. These timing arcs can be disabled in a variety of ways:

Using SDC:

set_disable_timing [-from ] [-to ][+]

Using RC native:

set_attr enabled false [find [ find / -libcell xyz] -libarc Q*/D*]

Obviously, you want to make sure your design guarantees that you will never operate your memories in that mode since otherwise this timing violation would be real.

good luck,
gh-
madhun
Posts: 2
Online: User is Offline
8/31/2007 12:58 AM  
As commented by gh this may be a case of AWT. The best way is indeed to disable the offending arcs.
 Another check you can make is by opening your libery files for the memory and grep for "mode" statement, you are then likely so see a functional mode and  AWT mode, for now RC does not recognize the mode statement. The presence of mode statements further will confirm that you can not solve this problem by setting consatants on test mode pins but only by disabling arcs.
-Madhu
Stalker
Posts: 24
Online: User is Offline
9/02/2007 12:46 AM  
Thanks to all,
I noticed, that case_analysis throuth AWT was missing in the latest release, I will add it back.
Maxim R.
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Forums > Digital IC > Synthesis and test > RC see paths through the memories.


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