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Subject: setting rc constraints
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alexsieh
Posts: 7
Online: User is Offline
9/21/2007 1:59 PM  
Hello designers,

I would like to simulate a variable ring oscillator with .sdf, but the rtl compiler is optimizing the design during the elaboration step impeding me to simulate it later on with .sdf.
Is there a way to preserve my module so that the rtl compiler will not optimize my series of inverters?

Thank you,

grasshopper
Posts: 48
Online: User is Offline
9/21/2007 2:05 PM  
Hi alexsieh,

sounds like you want to use the preserve attribute. Try

> get_attr -h preserve *

for detailed information

gh-
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Forums > Digital IC > Synthesis and test > setting rc constraints


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